PIC12F1822-I/MF Microchip Technology, PIC12F1822-I/MF Datasheet - Page 391

• Manufacturer Part Number: PIC12F1822-I/MF
• Description: IC, 8BIT MCU, PIC12, 32MHZ, DFN-8
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-I/MF

• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 32MHz
• No. Of Timers: 3
• Core Size: 8 Bit
• Program Memory Size: 3.5KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Extended Instruction Set
F
Fail-Safe Clock Monitor....................................................... 66
Firmware Instructions........................................................ 319
Fixed Voltage Reference (FVR) ........................................ 131
Flash Program Memory .................................................... 103
FSR Register .......... 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41
FVRCON (Fixed Voltage Reference Control) Register ..... 132
I
I
INDF Register ......... 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41
Indirect Addressing ............................................................. 45
Instruction Format ............................................................. 320
Instruction Set ................................................................... 319
 2010 Microchip Technology Inc.
2
C Mode (MSSPx)
Synchronous Master Mode ............................... 300, 304
Synchronous Slave Mode
ADDFSR ................................................................... 323
Fail-Safe Condition Clearing ....................................... 66
Fail-Safe Detection ..................................................... 66
Fail-Safe Operation..................................................... 66
Reset or Wake-up from Sleep..................................... 66
Associated Registers ................................................ 132
Erasing...................................................................... 108
Modifying................................................................... 112
Writing....................................................................... 108
Acknowledge Sequence Timing................................ 265
Bus Collision
Effects of a Reset...................................................... 266
I
Master Mode
Multi-Master Communication, Bus Collision
Multi-Master Mode .................................................... 266
Read/Write Bit Information (R/W Bit) ........................ 242
Slave Mode
Sleep Operation ........................................................ 266
Stop Condition Timing............................................... 265
ADDLW ..................................................................... 323
ADDWF..................................................................... 323
ADDWFC .................................................................. 323
ANDLW ..................................................................... 323
ANDWF..................................................................... 323
BRA........................................................................... 324
CALL ......................................................................... 325
CALLW...................................................................... 325
LSLF ......................................................................... 327
LSRF......................................................................... 327
2
C Clock Rate w/BRG.............................................. 273
Associated Registers
Reception.......................................................... 302
Transmission .................................................... 300
Associated Registers
Reception.......................................................... 305
Transmission .................................................... 304
During a Repeated Start Condition ................... 270
During a Stop Condition.................................... 271
Operation .......................................................... 257
Reception.......................................................... 263
Start Condition Timing .............................. 259, 260
Transmission .................................................... 261
and Arbitration .................................................. 266
Transmission .................................................... 247
Receive..................................................... 303
Transmit.................................................... 301
Receive..................................................... 305
Transmit.................................................... 304
PIC12F/LF1822/16F/LF1823
Preliminary
INTCON Register................................................................ 89
Internal Oscillator Block
Internal Sampling Switch (R
Internet Address ............................................................... 395
Interrupt-On-Change......................................................... 127
Interrupts ............................................................................ 83
INTOSC Specifications ..................................................... 349
IOCAF Register ................................................................ 128
IOCAN Register ................................................................ 128
IOCAP Register ................................................................ 128
L
LATA Register .......................................................... 122, 125
Load Conditions................................................................ 347
LSLF ................................................................................. 327
LSRF ................................................................................ 327
M
Master Synchronous Serial Port. See MSSPx
MCLR ................................................................................. 78
MOVF ....................................................................... 327
MOVIW ..................................................................... 328
MOVLB ..................................................................... 328
MOVWI ..................................................................... 329
OPTION.................................................................... 329
RESET...................................................................... 329
SUBWFB .................................................................. 331
TRIS ......................................................................... 332
BCF .......................................................................... 324
BSF........................................................................... 324
BTFSC...................................................................... 324
BTFSS ...................................................................... 324
CALL......................................................................... 325
CLRF ........................................................................ 325
CLRW ....................................................................... 325
CLRWDT .................................................................. 325
COMF ....................................................................... 325
DECF........................................................................ 325
DECFSZ ................................................................... 326
GOTO ....................................................................... 326
INCF ......................................................................... 326
INCFSZ..................................................................... 326
IORLW ...................................................................... 326
IORWF...................................................................... 326
MOVLW .................................................................... 328
MOVWF.................................................................... 328
NOP.......................................................................... 329
RETFIE..................................................................... 330
RETLW ..................................................................... 330
RETURN................................................................... 330
RLF........................................................................... 330
RRF .......................................................................... 331
SLEEP ...................................................................... 331
SUBLW..................................................................... 331
SUBWF..................................................................... 331
SWAPF..................................................................... 332
XORLW .................................................................... 332
XORWF .................................................................... 332
INTOSC
Associated Registers................................................ 129
ADC .......................................................................... 138
Associated registers w/ Interrupts .............................. 94
Configuration Word w/ Clock Sources........................ 70
Configuration Word w/ Reference Clock Sources ...... 73
TMR1........................................................................ 176
Specifications ................................................... 349
SS
) Impedance ..................... 143
DS41413A-page 391