PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 180

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
TABLE 12-9:
TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
DS39960D-page 180
PORTE
LATE
TRISE
PADCFG1
ODCON1
ODCON2
Legend: Shaded cells are not used by PORTE.
Note 1:
RE7/ECCP2/
P2A/AD15
Legend:
Note 1:
Pin Name
Name
2:
2:
Unimplemented on PIC18FX5K22 devices, read as ‘0’.
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode.
This feature is only available on PIC18F8XKXX devices.
CCP10OD
SSP1OD
TRISE7
LATE7
RDPU
Bit 7
ECCP2
RE7
PORTE FUNCTIONS (CONTINUED)
Function
AD15
RE7
P2A
(2)
(1)
(1)
CCP9OD
CCP2OD
Setting
TRISE6
LATE6
REPU
TRIS
Bit 6
RE6
0
1
0
1
0
x
x
(1)
I/O
O
O
O
O
I
I
I
CCP1OD
CCP8OD
TRISE5
RJPU
LATE5
Bit 5
RE5
Type
DIG
DIG
DIG
TTL
I/O
ST
ST
—
(2)
CCP7OD CCP6OD
LATE<7> data output.
PORTE<7> data input.
ECCP2 compare/PWM output; takes priority over port data.
ECCP2 capture input.
ECCP2 PWM Output A.
May be configured for tri-state during Enhanced PWM shutdown event.
External memory interface, Address/Data Bit 15 output.
External memory interface, Data Bit 15 input.
TRISE4
LATE4
Bit 4
RE4
—
—
TRISE3
LATE3
Bit 3
RE3
—
—
RTSECSEL1 RTSECSEL0
CCP5OD
TRISE2
Description
LATE2
Bit 2
RE2
 2009-2011 Microchip Technology Inc.
—
CCP4OD
TRISE1
LATE1
Bit 1
RE1
—
CCP3OD
SSP2OD
TRISE0
LATE0
Bit 0
RE0
—