PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 60

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
4.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the LF-INTOSC source, this
mode provides the best power conservation of all the
Run modes, while still executing code. It works well for
user applications which are not highly timing-sensitive
or do not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block – either LF-INTOSC or INTOSC (MF-INTOSC or
HF-INTOSC) – there are no distinguishable differences
between the PRI_RUN and RC_RUN modes during
execution. Entering or exiting RC_RUN mode, how-
ever, causes a clock switch delay. Therefore, if the
primary clock source is the internal oscillator block,
using RC_RUN mode is not recommended.
This mode is entered by setting the SCS1 bit to ‘1’. To
maintain software compatibility with future devices, it is
recommended that the SCS0 bit also be cleared, even
though the bit is ignored. When the clock source is
switched to the INTOSC multiplexer (see
TABLE 4-3:
DS39960D-page 60
IRCF<2:0>
Non-Zero
Non-Zero
000
000
000
RC_RUN MODE
INTERNAL OSCILLATOR FREQUENCY STABILITY BITS
INTSRC
0
1
1
x
x
MFIOSEL
Figure
x
0
1
0
1
4-3),
MFIOFS = 0, HFIOFS = 0 and clock source is LF-INTOSC
MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
Status of MFIOFS or HFIOFS when INTOSC is Stable
the primary oscillator is shut down and the OSTS bit is
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output (HF-INTOSC/MF-INTOSC) is not
enabled and the HFIOFS and MFIOFS bits will remain
clear. There will be no indication of the current clock
source. The LF-INTOSC source is providing the device
clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), or if INTSRC or
MFIOSEL is set, the HFIOFS or MFIOFS bit is set after
the INTOSC output becomes stable. For details, see
Table
Note:
4-3.
Caution should be used when modifying a
single IRCF bit. At a lower V
possible to select a higher clock speed
than is supportable by that V
device operation may result if the V
F
OSC
specifications are violated.
 2009-2011 Microchip Technology Inc.
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