PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 464
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F85K22-I/PT
Manufacturer Part Number
PIC18F85K22-I/PT
Description
IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F85K22-IPT.pdf
(550 pages)
Specifications of PIC18F85K22-I/PT
Controller Family/series
PIC18
No. Of I/o's
69
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
64MHz
No. Of Timers
8
Core Size
8 Bit
Program Memory Size
32KB
Core Processor
PIC
Speed
64MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F85K22-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F85K22-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F85K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87K22 FAMILY
RLNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39960D-page 464
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
=
=
register ‘f’
Rotate Left f (No Carry)
0 f 255
d [0,1]
a [0,1]
(f<n>) dest<n + 1 >,
(f<7>) dest<0>
N, Z
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘ 0 ’, the result
is placed in W. If ‘d’ is ‘ 1 ’, the result is
stored back in register ‘f’.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
RLNCF
RLNCF
Read
Q2
0100
1010 1011
0101 0111
f {,d {,a}}
01da
Process
REG, 1, 0
Data
register f
Q3
ffff
for details.
destination
Write to
Q4
ffff
RRCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
=
=
=
=
=
register ‘f’
2009-2011 Microchip Technology Inc.
Rotate Right f through Carry
RRCF
0 f 255
d [0,1]
a [0,1]
(f<n>) dest<n – 1 >,
(f<0>) C,
(C) dest<7>
C, N, Z
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘ 0 ’, the result is placed in W.
If ‘d’ is ‘ 1 ’, the result is placed back in
register ‘f’.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
RRCF
Read
0011
Q2
1110 0110
0
1110 0110
0111 0011
0
C
f {,d {,a}}
00da
Process
REG, 0, 0
Data
Q3
register f
ffff
for details.
destination
Write to
Q4
ffff
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