PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 450
PIC18F85K22-I/PT
Manufacturer Part Number
PIC18F85K22-I/PT
Description
IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F85K22-IPT.pdf
(550 pages)
Specifications of PIC18F85K22-I/PT
Controller Family/series
PIC18
No. Of I/o's
69
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
64MHz
No. Of Timers
8
Core Size
8 Bit
Program Memory Size
32KB
Core Processor
PIC
Speed
64MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F85K22-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F85K22-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F85K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 450 of 550
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PIC18F87K22 FAMILY
DAW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
DS39960D-page 450
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
W
C
DC
W
C
DC
W
C
DC
W
C
DC
Q1
=
=
=
=
=
=
=
=
=
=
=
=
register W
Decimal Adjust W Register
DAW
None
If [W<3:0> > 9] or [DC = 1 ], then
(W<3:0>) + 6 W<3:0>;
else
(W<3:0>) W<3:0>
If [W<7:4> > 9] or [C = 1 ], then
(W<7:4>) + 6 W<7:4>;
C = 1 ;
else
(W<7:4>) W<7:4>
C
DAW adjusts the 8-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
1
1
DAW
Read
0000
Q2
A5h
0
0
05h
1
0
CEh
0
0
34h
1
0
0000
Process
Data
Q3
0000
Write
Q4
W
0111
DECF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
CNT
Z
CNT
Z
Q1
=
=
=
=
register ‘f’
2009-2011 Microchip Technology Inc.
Decrement f
DECF f {,d {,a}}
0 f 255
d [0,1]
a [0,1]
(f) – 1 dest
C, DC, N, OV, Z
Decrement register, ‘f’. If ‘d’ is ‘ 0 ’, the
result is stored in W. If ‘d’ is ‘ 1 ’, the
result is stored back in register ‘f’.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
DECF
Read
0000
Q2
01h
0
00h
1
CNT,
01da
Process
Data
Q3
1, 0
ffff
for details.
destination
Write to
Q4
ffff
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