PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 295

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 21-6:
REGISTER 21-7:
 2009-2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
R/W-0
GCEN
R/W-1
MSK7
2:
If the I
writes to the SSPxBUF are disabled).
This register shares the same SFR address as SSPxADD and is only addressable in select MSSPx
operating modes. See
MSK0 is not used as a mask bit in 7-bit addressing.
GCEN: General Call Enable bit
1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address is disabled
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit.
0 = Acknowledge sequence is Idle
RCEN: Receive Enable bit (Master Receive mode only)
1 = Enables Receive mode for I
0 = Receive is Idle
PEN: Stop Condition Enable bit
1 = Initiates Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition is Idle
RSEN: Repeated Start Condition Enable bit
1 = Initiates Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition is Idle
SEN: Stretch Enable bit
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
MSK<7:0>: Slave Address Mask Select bit
1 = Masking of corresponding bit of SSPxADD is enabled
0 = Masking of corresponding bit of SSPxADD is disabled
ACKSTAT
2
R/W-0
C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or
R/W-1
MSK6
Automatically cleared by hardware.
SSPxCON2: MSSPx CONTROL REGISTER 2 (I
SSPxMSK: I
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
ACKDT
R/W-0
R/W-1
MSK5
Section 21.4.3.4 “7-Bit Address Masking Mode”
2
C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)
(1)
(1)
ACKEN
(1)
2
C
R/W-0
R/W-1
MSK4
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
PIC18F87K22 FAMILY
RCEN
R/W-0
R/W-1
MSK3
(1)
(1)
(1)
2
PEN
R/W-0
R/W-1
MSK2
C™ SLAVE MODE)
(1)
for more details.
x = Bit is unknown
x = Bit is unknown
RSEN
R/W-0
R/W-1
MSK1
(1)
DS39960D-page 295
MSK0
SEN
R/W-0
R/W-1
(1)
(2)
bit 0
bit 0
(1)