PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 279

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.4.8
In Sleep mode, all clock sources are disabled.
Timer2/4/6/8 will not increment and the state of the
module will not change. If the ECCPx pin is driving a
value, it will continue to drive that value. When the
device wakes up, it will continue from this state. If
Two-Speed Start-ups are enabled, the initial start-up
frequency from HF-INTOSC and the postscaler may
not be immediately stable.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCPx module without change.
TABLE 20-4:
 2009-2011 Microchip Technology Inc.
INTCON
RCON
PIR3
PIR4
PIE3
PIE4
IPR3
IPR4
TRISB
TRISC
TRISE
TRISH
TMR1H
TMR1L
TMR2
TMR3H
TMR3L
TMR4
TMR6
TMR8
TMR10
TMR12
PR2
PR4
PR6
PR8
PR10
PR12
Note 1:
File Name
(1)
(1)
2:
(2)
(1)
(1)
Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22).
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
OPERATION IN POWER-MANAGED
MODES
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer3 Register High Byte
Timer3 Register Low Byte
Timer4 Register
Timer6 Register
Timer8 Register
TMR10 Register
TMR10 Register
Timer2 Period Register
Timer4 Period Register
Timer6 Period Register
Timer8 Period Register
Timer10 Period Register
Timer12 Period Register
CCP10IF
CCP10IE
CCP10IP
GIE/GIEH
TMR5GIF
TMR5GIE
TMR5GIP
TRISB7
TRISC7
TRISE7
TRISH7
REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND
TIMER1/2/3/4/6/8/10/12
IPEN
Bit 7
(1)
(1)
(1)
CCP9IE
CCP9IP
PEIE/GIEL
CCP9IF
SBOREN
TRISB6
TRISC6
TRISE6
TRISH6
Bit 6
—
—
—
(1)
(1)
(1)
TMR0IE
CCP8IE
CCP8IP
CCP8IF
TRISB5
TRISC5
TRISE5
TRISH5
RC2IF
RC2IE
RC2IP
Bit 5
CM
CCP7IF
CCP7IE
CCP7IP
TRISB4
TRISC4
TRISE4
TRISH4
INT0IE
TX2IE
TX2IP
TX2IF
Bit 4
PIC18F87K22 FAMILY
RI
20.4.8.1
If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock
failure will force the device into the power-managed
RC_RUN mode and the OSCFIF bit of the PIR2 register
will be set. The ECCPx will then be clocked from the
internal oscillator clock source, which may have a
different clock frequency than the primary clock.
20.4.9
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states. This forces the ECCP module to reset to
a state compatible with previous, non-Enhanced CCP
modules used on other PIC18 and PIC16 devices.
CTMUIE
CTMUIP
CTMUIF
CCP6IF
CCP6IE
CCP6IP
TRISC3
TRISH3
TRISB3
TRISE3
RBIE
Bit 3
TO
EFFECTS OF A RESET
Operation with Fail-Safe
Clock Monitor (FSCM)
TMR0IF
CCP2IF
CCP5IF
CCP2IE
CCP5IE
CCP2IP
CCP5IP
TRISB2
TRISC2
TRISE2
TRISH2
Bit 2
PD
CCP1IE
CCP4IE
CCP1IP
CCP4IP
CCP1IF
CCP4IF
TRISB1
TRISC1
TRISE1
TRISH1
INT0IF
Bit 1
POR
DS39960D-page 279
RTCCIE
RTCCIP
RTCCIF
CCP3IF
CCP3IE
CCP3IP
TRISC0
TRISH0
TRISB0
TRISE0
RBIF
Bit 0
BOR