AU80610004671AAS LBMH Intel, AU80610004671AAS LBMH Datasheet - Page 130
AU80610004671AAS LBMH
Manufacturer Part Number
AU80610004671AAS LBMH
Description
MPU, ATOM PROCESSOR, D410, FC-BGA8
Manufacturer
Intel
Series
ATOM - D400r
Datasheet
1.AU80610004392AAS_LBLA.pdf
(153 pages)
Specifications of AU80610004671AAS LBMH
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Operating Temperature Range
0°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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LBB - LBB-Legacy Backlight Brightness
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
This register can be accessed by either Byte, Word, or Dword PCI config cycles. A
write to this register will cause the Backlight Event (Display B Interrupt) if enabled
PCI Device 2 Function 1
Vendor
Identification
Device
Identification
PCI Command
PCI Status
Revision
Identification
Class Code
Register
Cache Line
Size
Master Latency
Timer
Header Type
31:24
23:16
15:8
7:0
Bit
Register
Name
Access
RW
RW
RW
RW
VID2
DID2
PCICMD2
PCISTS2
RID2
CC
CLS
MLT2
HDR2
Register
Symbol
Default
Value
00h
00h
00h
00h
2
8
0
4
6
9
C
D
E
Reserved
Reserved
LBPC Scratch Trigger1
(LBPC_SCRATCH_1):
When written, this scratch byte triggers an
interrupt when LBEE is enabled in the Pipe B
Status register and the Display B Event is
enabled in IER and unmasked in IMR etc. If
written as part of a 16-bit or 32-bit write, only
one interrupt is generated in common.
Reserved
Register
Start
0/2/0/PCI
F4-F7h
00000000h
32 bits
0h
RW;
1
3
5
7
8
B
C
D
E
Register
End
Processor Configuration Registers
Description
8086h
A002h
0000h
0090h
02h
038000h
00h
00h
80h
Default Value
RO;
RO;
RO; RW;
RO;
RO;
RO;
RO;
RO;
RO;
Access
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