AU80610004671AAS LBMH Intel, AU80610004671AAS LBMH Datasheet - Page 45

• Manufacturer Part Number: AU80610004671AAS LBMH
• Description: MPU, ATOM PROCESSOR, D410, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D400r

Specifications of AU80610004671AAS LBMH

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
Datasheet
Note: The CPU Uncore may hang if a PCI Express Graphics Attach or DMI originated access
RE - Read Enable. When RE = 1, the CPU read accesses to the corresponding memory
segment are claimed by the CPU Uncore and directed to main memory. Conversely,
when RE = 0, the host read accesses are directed to PCI_A.
WE - Write Enable. When WE = 1, the host write accesses to the corresponding
memory segment are claimed by the CPU Uncore and directed to main memory.
Conversely, when WE = 0, the host write accesses are directed to PCI_A.
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0,
the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in
size.
For these reasons the following critical restriction is placed on the programming of the
PAM regions: At the time that a DMI or PCI Express Graphics Attach accesses to the
PAM region may occur, the targeted PAM segment must be programmed to be both
readable and writeable.
to Read Disabled or Write Disabled PAM segments occur (due to a possible IWB to
non-DRAM).
7:6
5:4
3:0
Bit
Access
RW/L
RO
RO
Default
Value
00b
00b
0h
RST/
PWR
Core
Core
Core
00:
to DMI.
01:
All writes are forwarded to DMI.
10:
Reads are serviced by DMI.
11:
writes are serviced by DRAM.
Reserved ()
0F0000-0FFFFF Attribute (HIENABLE):
write cycles that address the BIOS area from
0F0000 to 0FFFFF.
Reserved ()
This field controls the steering of read and
DRAM Disabled: All accesses are directed
Read Only: All reads are sent to DRAM.
Write Only: All writes are sent to DRAM.
Normal DRAM Operation: All reads and
Description
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