PIC12F1822-I/SN Microchip Technology, PIC12F1822-I/SN Datasheet - Page 206

• Manufacturer Part Number: PIC12F1822-I/SN
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-I/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of I/o's: 6
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 128Byte
• Embedded Interface Type: AUSART, EUSART, I2C, SPI
• No. Of Pins: 8
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Processor Series: PIC12F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
24.2
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPR1H:CCPR1L
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
• Toggle the CCP1 output
• Set the CCP1 output
• Clear the CCP1 output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCP1M<3:0> control bits of the CCP1CON register. At
the same time, the interrupt flag CCP1IF bit is set.
All Compare modes can generate an interrupt.
Figure 24-2
Compare operation.
FIGURE 24-2:
24.2.1
The user must configure the CCP1 pin as an output by
clearing the associated TRIS bit.
Also, the CCP1 pin function may be moved to
alternative pins using the APFCON register. Refer to
Section 12.1 “Alternate Pin Function”
details.
DS41413B-page 206
Note:
CCP1
Pin
Output Enable
TRIS
Compare Mode
CCP1 PIN CONFIGURATION
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the PORT I/O
data latch.
shows a simplified diagram of the
Q
Special Event Trigger
CCP1M<3:0>
R
S
Mode Select
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
Set CCP1IF Interrupt Flag
4
(PIR1)
Match
CCPR1H CCPR1L
TMR1H
Comparator
for more
TMR1L
Preliminary
24.2.2
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
See
for more information on configuring Timer1.
24.2.3
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 module does not
assert control of the CCP1 pin (see the CCP1CON
register).
24.2.4
When Special Event Trigger mode is chosen
(CCP1M<3:0> = 1011), the CCP1 module does the
following:
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
The CCP1 module does not assert control of the CCP1
pin in this mode.
The Special Event Trigger output of the CCP1 occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPR1H, CCPR1L regis-
ter pair. The TMR1H, TMR1L register pair is not reset
until the next rising edge of the Timer1 clock. The Spe-
cial Event Trigger output starts an A/D conversion (if
the A/D module is enabled). This allows the CCPR1H,
CCPR1L register pair to effectively provide a 16-bit pro-
grammable period register for Timer1.
TABLE 24-3:
Refer to
(ADC) Module”
PIC12F/LF1822/16F/LF1823
Note:
Note 1: The Special Event Trigger from the CCP
Section 21.0 “Timer1 Module with Gate Control”
2: Removing
Section 16.0 “Analog-to-Digital Converter
TIMER1 MODE RESOURCE
Clocking Timer1 from the system clock
(F
mode. In order for Compare mode to
recognize the trigger event on the CCP1
pin, TImer1 must be clocked from the
instruction clock (F
external clock source.
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Device
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates
preclude the Reset from occurring.
OSC
for more information.
) should not be used in Compare
SPECIAL EVENT TRIGGER
 2010 Microchip Technology Inc.
the
the
match
Timer1
OSC
CCP1/ECCP1
/4) or from an
condition
CCP1
Reset,
will
by