PIC12F1822-I/SN Microchip Technology, PIC12F1822-I/SN Datasheet - Page 311

• Manufacturer Part Number: PIC12F1822-I/SN
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-I/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of I/o's: 6
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 128Byte
• Embedded Interface Type: AUSART, EUSART, I2C, SPI
• No. Of Pins: 8
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Processor Series: PIC12F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

26.4.2.3
The operation of the Synchronous Master and Slave
modes is identical
Master
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 26-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
 2010 Microchip Technology Inc.
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
TRISA
TRISC
TXSTA
Legend:
Note 1:
never Idle
Name
(2)
2:
Reception”), with the following exceptions:
*
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
Page provides register information.
PIC12F/LF1822 only.
PIC16F/LF1823 only.
EUSART Synchronous Slave
Reception
TMR1GIE
TMR1GIF
ABDOVF
CSRC
SPEN
RECEPTION
Bit 7
GIE
—
—
(Section 26.4.1.5 “Synchronous
RCIDL
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
—
—
PIC12F/LF1822/PIC16F/LF1823
TRISA5
TMR0IE
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
—
EUSART Receive Data Register
(1)
TRISA4
Preliminary
TRISC4
CREN
SYNC
SCKP
INTE
Bit 4
TXIE
TXIF
(1)
TRISC3
ADDEN
TRISA3
SENDB
BRG16
SSPIE
SSPIF
IOCIE
26.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
Bit 3
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for both the CK and DT pins
(if applicable).
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISC2
BRGH
FERR
Bit 2
—
Synchronous Slave Reception
Set-up:
TMR2IE
TMR2IF
TRISA1
TRISC1
OERR
TRMT
WUE
Bit 1
INTF
TMR1IE
TMR1IF
TRISC0
ABDEN
TRISA0
IOCIF
RX9D
TX9D
Bit 0
DS41413B-page 311
Register
on Page
290*
296
101
102
105
295
124
128
294