PIC12F1822-I/SN Microchip Technology, PIC12F1822-I/SN Datasheet - Page 280

• Manufacturer Part Number: PIC12F1822-I/SN
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-I/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of I/o's: 6
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 128Byte
• Embedded Interface Type: AUSART, EUSART, I2C, SPI
• No. Of Pins: 8
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Processor Series: PIC12F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
REGISTER 25-1:
DS41413B-page 280
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0/0
SMP
SMP: SPI Data Input Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
(I
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
S: Start bit
(I
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
R/W: Read/Write bit information (I
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
In I
1 = Read
0 = Write
In I
1 = Transmit is in progress
0 = Transmit is not in progress
UA: Update Address bit (10-bit I
1 = Indicates that the user needs to update the address in the SSP1ADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSP1BUF is full
0 = Receive not complete, SSP1BUF is empty
Transmit (I
1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty
2
2
C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.)
C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.)
R/W-0/0
2
2
2
2
C Master or Slave mode:
C™ mode only:
C Slave mode:
C Master mode:
CKE
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP1 is in Idle mode.
SSP1STAT: SSP1 STATUS REGISTER
2
C mode only):
W = Writable bit
‘0’ = Bit is cleared
x = Bit is unknown
2
C modes):
R-0/0
D/A
2
C mode only)
2
C mode only)
2
C mode only)
R-0/0
Preliminary
P
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R-0/0
S
R-0/0
R/W
 2010 Microchip Technology Inc.
R-0/0
UA
R-0/0
BF
bit 0