PIC12F1822-I/SN Microchip Technology, PIC12F1822-I/SN Datasheet - Page 330

• Manufacturer Part Number: PIC12F1822-I/SN
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-I/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of I/o's: 6
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 128Byte
• Embedded Interface Type: AUSART, EUSART, I2C, SPI
• No. Of Pins: 8
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Processor Series: PIC12F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
TABLE 29-3:
DS41413B-page 330
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
ADDFSR
MOVIW
MOVWI
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
Mnemonic,
Operands
2:
3:
is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
See Table in the MOVIW and MOVWI instruction descriptions.
k
–
k
–
k
k
k
–
–
–
–
–
–
f
n, k
n mm
k[n]
n mm
k[n]
PIC12F/LF1822/16F/LF1823 ENHANCED INSTRUCTION SET (CONTINUED)
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
Add Literal k to FSRn
Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
Move W to INDFn, Indexed Indirect.
Description
C-COMPILER OPTIMIZED
INHERENT OPERATIONS
CONTROL OPERATIONS
Preliminary
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
Cycles
11
00
10
00
10
00
11
00
00
00
00
00
00
00
MSb
11
00
11
00
11
14-Bit Opcode
001k
0000
0kkk
0000
1kkk
0000
0100
0000
0000
0000
0000
0000
0000
0000
0001
0000
1111
0000
1111
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
0110
0000
0110
0000
0110
0110
0nkk
1nkk
0nkk
0001
0001
 2010 Microchip Technology Inc.
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
0100
0000
0010
0001
0011
0fff
0nmm
kkkk
kkkk
kkkk
1nmm
LSb
TO, PD
TO, PD
Z
Z
Affected
Status
2, 3
2
2, 3
2
Notes