P89LPC912FDH NXP Semiconductors, P89LPC912FDH Datasheet - Page 31

• Manufacturer Part Number: P89LPC912FDH
• Description: MCU 8BIT 80C51 1K FLASH, TSSOP14
• Manufacturer: NXP Semiconductors

Specifications of P89LPC912FDH

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 12
• Program Memory Size: 1KB
• Ram Memory Size: 128Byte
• Cpu Speed: 18MHz
• Oscillator Type: External, Internal
• No. Of Timers: 4
• No. Of: RoHS Compliant

NXP Semiconductors
P89LPC912_913_914_5
Product data sheet
8.10 Memory organization
8.7 CCLK wake-up delay
8.8 CCLK modification: DIVM register
8.9 Low power select
The P89LPC912/913/914 has an internal wake-up timer that delays the clock until it
stabilizes depending on the clock source used. If the clock source is any of the three
crystal selections (P89LPC912, P89LPC913) the delay is 992 OSCCLK cycles plus 60 s
to 100 s. If the clock source is either the internal RC oscillator, watchdog oscillator, or
external clock, the delay is 224 OSCCLK cycles plus 60 s to 100 s.
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
The P89LPC912 and P89LPC913 are designed to run at 18 MHz (CCLK) maximum.
However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1
to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz or
slower.
The various P89LPC912/913/914 memory spaces are as follows:
Fig 12. Block diagram of oscillator control (P89LPC914)
SPI
(400 kHz
(7.3728 MHz
OSCILLATOR
OSCILLATOR
WATCHDOG
Rev. 05 — 28 September 2007
RC
30 %
TIMER 0/
1 %)
TIMER 1
20 %)
rcclk
8-bit microcontrollers with two-clock 80C51 core
pclk
oscclk
P89LPC912/913/914
DIVM
GENERATOR
BAUDRATE
cclk
pclk
2
© NXP B.V. 2007. All rights reserved.
WDT
RTC
CPU
UART
002aaa483
31 of 66