P89LPC912FDH NXP Semiconductors, P89LPC912FDH Datasheet - Page 34

• Manufacturer Part Number: P89LPC912FDH
• Description: MCU 8BIT 80C51 1K FLASH, TSSOP14
• Manufacturer: NXP Semiconductors

Specifications of P89LPC912FDH

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 12
• Program Memory Size: 1KB
• Ram Memory Size: 128Byte
• Cpu Speed: 18MHz
• Oscillator Type: External, Internal
• No. Of Timers: 4
• No. Of: RoHS Compliant

NXP Semiconductors
P89LPC912_913_914_5
Product data sheet
8.12.1 Port configurations
8.12.2 Quasi-bidirectional output configuration
Table 10.
[1]
The P89LPC914 has three I/O ports: Port 0, Port 1, and Port 2. The exact number of I/O
pins available depends upon the reset option chosen, as shown in
Table 11.
[1]
Except as listed below, every I/O pin on the P89LPC912/913/914 may be configured by
software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard
80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for
each port select the output type for each port pin.
P1.5/RST can only be an input and cannot be configured.
P1.2/T0 may only be configured to be either input-only or open drain (P89LPC912,
P89LPC914).
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
The P89LPC912/913/914 is a 3 V device, but the pins are 5 V-tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing
from the pin to V
quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch
suppression circuit.
Clock source
On-chip oscillator or watchdog
oscillator
External clock input
Low/medium/high-speed oscillator
(external crystal or resonator)
Reset option
No external reset (except during power-up)
External RST pin supported
Required for operation above 12 MHz.
Required for operation above 12 MHz.
Number of I/O pins available (P89LPC912, P89LPC913)
Number of I/O pins available (P89LPC914)
DD
, causing extra power consumption. Therefore, applying 5 V in
Rev. 05 — 28 September 2007
[1]
Reset option
No external reset (except during power-up) 12
External RST pin supported
No external reset (except during power-up) 11
External RST pin supported
No external reset (except during power-up) 10
External RST pin supported
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
Number of I/O pins
(14-pin package)
12
11
[1]
Table
© NXP B.V. 2007. All rights reserved.
11.
Number of
I/O pins
(14-pin
package)
11
10
9
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