P89LPC912FDH NXP Semiconductors, P89LPC912FDH Datasheet - Page 39

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P89LPC912FDH

Manufacturer Part Number
P89LPC912FDH
Description
MCU 8BIT 80C51 1K FLASH, TSSOP14
Manufacturer
NXP Semiconductors
Datasheet

Specifications of P89LPC912FDH

Controller Family/series
(8051) 8052
Core Size
8bit
No. Of I/o's
12
Program Memory Size
1KB
Ram Memory Size
128Byte
Cpu Speed
18MHz
Oscillator Type
External, Internal
No. Of Timers
4
No. Of
RoHS Compliant

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NXP Semiconductors
P89LPC912_913_914_5
Product data sheet
8.16.4 Mode 3
8.16.5 Mode 6 (P89LPC912, P89LPC914)
8.16.6 Timer overflow toggle output (P89LPC912, P89LPC914)
8.18.1 Mode 0
8.17 RTC/system timer
8.18 UART (P89LPC913, P89LPC914)
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is
in Mode 3 it can still be used by the serial port as a baud rate generator.
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
Timers 0 can be configured to automatically toggle the T0 output whenever a timer
overflow occurs. The same device pins that are used for the T0 count input is also used for
the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow
when this mode is turned on.
The P89LPC912/913/914 devices have a simple RTC that allows a user to continue
running an accurate timer while the rest of the device is powered-down. The RTC can be
a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit
prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will
be reloaded again and the RTCF flag will be set.
On the P89LPC914 the clock source for this counter is the CPU clock (CCLK). On the
P89LPC912 and P89LPC913 devices, the clock source for this counter can either be the
CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being
used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will
use CCLK as its clock source.
Only power-on reset will reset the RTC and its associated SFRs to the default state.
The P89LPC913 and P89LPC914 devices have an enhanced UART that is compatible
with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a
baud rate source. The P89LPC913 does include an independent Baud Rate Generator.
The baud rate can be selected from the oscillator (divided by a constant), Timer 1
overflow, or the independent Baud Rate Generator. In addition to the baud rate
generation, enhancements over the standard 80C51 UART include Framing Error
detection, automatic address recognition, selectable double buffering and several interrupt
options. The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART,
and CCLK/32 or CCLK/16.
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at
frequency.
Rev. 05 — 28 September 2007
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
1
16
of the CPU clock
© NXP B.V. 2007. All rights reserved.
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