P89LPC912FDH NXP Semiconductors, P89LPC912FDH Datasheet - Page 48

• Manufacturer Part Number: P89LPC912FDH
• Description: MCU 8BIT 80C51 1K FLASH, TSSOP14
• Manufacturer: NXP Semiconductors

Specifications of P89LPC912FDH

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 12
• Program Memory Size: 1KB
• Ram Memory Size: 128Byte
• Cpu Speed: 18MHz
• Oscillator Type: External, Internal
• No. Of Timers: 4
• No. Of: RoHS Compliant

NXP Semiconductors
P89LPC912_913_914_5
Product data sheet
8.26.1 Software reset
8.26.2 Dual data pointers
8.27.1 General description
8.27.2 Features
8.27.3 Flash organization
8.26 Additional features
8.27 Flash program memory
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
The P89LPC912/913/914 flash memory provides in-circuit electrical erasure and
programming. The flash can be erased, read, and written as bytes. The Sector and Page
Erase functions can erase any flash sector (256 B) or page (16 B). The Chip Erase
operation will erase the entire program memory. ICP using standard commercial
programmers is available. In addition, IAP and byte erase allows code memory to be used
for non-volatile data storage. On-chip erase and write timing generation contribute to a
user-friendly programming interface. The P89LPC912/913/914 flash reliably stores
memory contents even after 400000 erase and program cycles. The cell is designed to
optimize the erase and programming mechanisms. The P89LPC912/913/914 uses V
the supply voltage to perform the Program/Erase algorithms.
The P89LPC912/913/914 program memory consists of four 256 byte sectors. Each sector
can be further divided into 16 B pages. In addition to sector erase, page erase, and byte
erase, a 16 B page register is included which allows from 1 B to 16 B of a given page to
be programmed at the same time, substantially reducing overall programming time. In
addition, erasing and reprogramming of user-programmable configuration bytes including
UCFG1, the Boot Status Bit, and the Boot Vector is supported.
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Programming and erase over the full operating voltage range.
Byte erase allows code memory to be used for data storage.
Read/Programming/Erase using ICP.
Any flash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the flash for each sector.
400000 typical erase/program cycles for each byte.
20 year minimum data retention.
Rev. 05 — 28 September 2007
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
© NXP B.V. 2007. All rights reserved.
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