SAK-C505CA-4EMCA Infineon Technologies, SAK-C505CA-4EMCA Datasheet - Page 36

• Manufacturer Part Number: SAK-C505CA-4EMCA
• Description: IC, 8BIT MCU, 32K OTP, SMD
• Manufacturer: Infineon Technologies

Specifications of SAK-C505CA-4EMCA

• Core Size: 8bit
• No. Of I/o's: 34
• Program Memory Size: 32KB
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• Oscillator Type: External, Internal
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: MQFP
• Controller Family/series: C500
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Compare Mode 1
If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the
new value will not appear at the output pin until the next compare match occurs. Thus, it can be
choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.
In compare mode 1 (see
(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.
Figure 13
Compare Function in Compare Mode 1
Timer 2 Capture Modes
Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the
current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this
function.
In mode 0, the external event causing a capture is :
In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture
register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The timer 2
contents will be latched into the appropriate capture register in the cycle following the write
instruction. In this mode no interrupt request will be generated.
Data Sheet
– for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1
– for the CRC register:
Compare Register
Timer Register
Compare Reg.
Timer Circuit
Comparator
Circuit
16 Bit
16 Bit
Compare
Match
Figure
a positive or negative transition at the corresponding pin, depending
on the status of the bit I3FR in SFR T2CON.
13) the port circuit consists of two separate latches. One latch
Port Circuit
Internal
Bus
Write to
Latch
32
D
CLK
Shadow
Latch
Read Latch
Q
C505/C505C/C505A/C505CA
D
CLK
Latch
Port
Read Pin
Q
Q
V
DD
MCS02662
Port
Pin
12.00