SAK-C505CA-4EMCA Infineon Technologies, SAK-C505CA-4EMCA Datasheet - Page 59

• Manufacturer Part Number: SAK-C505CA-4EMCA
• Description: IC, 8BIT MCU, 32K OTP, SMD
• Manufacturer: Infineon Technologies

Specifications of SAK-C505CA-4EMCA

• Core Size: 8bit
• No. Of I/o's: 34
• Program Memory Size: 32KB
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• Oscillator Type: External, Internal
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: MQFP
• Controller Family/series: C500
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 12
Access Modes Selection
Access Mode
Program OTP memory byte
Read OTP memory byte
Program OTP lock bits
Read OTP lock bits
Read OTP version byte
Lock Bits Programming / Read
The C505A-4E/C505CA-4E has two programmable lock bits which, when programmed according
to
lock bits can also be read.
Table 13
Lock Bit Protection Types
Lock Bits at D1,D0
Data Sheet
D1
1
1
0
0
Table
13, provide four levels of protection for the on-chip OTP code memory. The state of the
D0
1
0
1
0
Protection
Level
Level 0
Level 1
Level 2
Level 3
EA/
V
V
V
V
V
V
PP
PP
PP
IH
IH
IH
Protection Type
The OTP lock feature is disabled. During normal operation of
the C505A-4E/C505CA-4E, the state of the EA pin is not
latched on reset.
During normal operation of the C505A-4E/C505CA-4E, MOVC
instructions executed from external program memory are
disabled from fetching code bytes from internal memory. EA is
sampled and latched on reset. An OTP memory read operation
is only possible using the ROM/OTP verification mode 2 for
protection level 1. Further programming of the OTP memory is
disabled (reprogramming security).
Same as level 1, but also OTP memory read operation using
OTP verification mode is disabled.
Same as level 2; but additionally external code execution by
setting EA=low during normal operation of the C505A-4E/
C505CA-4E is no more possible.
External code execution, which is initiated by an internal
program (e.g. by an internal jump instruction above the ROM
boundary), is still possible.
PROG
H
H
H
55
PRD
H
H
1
H
H
L
PMSEL
C505/C505C/C505A/C505CA
0
H
L
H
of sign. byte
Byte addr.
Address
(Port 2)
A8-14
A0-7
–
D1,D0 see
Table 13
(Port 0)
Data
D0-7
D0-7
12.00