SAK-C505CA-4EMCA Infineon Technologies, SAK-C505CA-4EMCA Datasheet - Page 50
![IC, 8BIT MCU, 32K OTP, SMD](/photos/19/7/190707/ge44mqfp05-40_sml.jpg)
SAK-C505CA-4EMCA
Manufacturer Part Number
SAK-C505CA-4EMCA
Description
IC, 8BIT MCU, 32K OTP, SMD
Manufacturer
Infineon Technologies
Datasheet
1.SAF-C505CA-LM.pdf
(88 pages)
Specifications of SAK-C505CA-4EMCA
Core Size
8bit
No. Of I/o's
34
Program Memory Size
32KB
Ram Memory Size
256Byte
Cpu Speed
20MHz
Oscillator Type
External, Internal
No. Of Timers
3
No. Of Pwm Channels
4
Digital Ic Case Style
MQFP
Controller Family/series
C500
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Fail Save Mechanisms
The C505 offers enhanced fail safe mechanisms, which allow an automatic recovery from software
upset or hardware failure :
The watchdog timer in the C505 is a 15-bit timer, which is incremented by a count rate of
upto
divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the
watchdog timer can be written.
Figure 24
Block Diagram of the Programmable Watchdog Timer
The watchdog timer can be started by software (bit SWDT in SFR IEN1) but it cannot be stopped
during active mode of the device. If the software fails to refresh the running watchdog timer an
internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the
content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh
sequence consists of two consequtive instructions which set the bits WDT and SWDT each. The
reset cause (external reset or reset caused by the watchdog) can be examined by software (flag
WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and
power down mode of the processor.
Data Sheet
– a programmable watchdog timer (WDT), with variable time-out period from 192 s up to
– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
f
approx. 393.2 ms at 16 MHz (314.5 ms at 20 MHz).
microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.
OSC
f
OWDS
OSC
External HW Reset
/192. The system clock of the C505 is divided by two prescalers, a divide-by-two and a
/ 6
SWDT
WDTS
WDT
2
Control Logic
WDT Reset - Request
Figure 24
16
shows the block diagram of the watchdog timer unit.
IP0 (A9 )
46
H
IEN0 (A8 )
IEN1 (B8 )
WDTPSEL
C505/C505C/C505A/C505CA
H
H
7
0
6
14
WDTREL (86 )
WDTL
WDTH
H
MCB03306
7
8
0
f
OSC
12.00
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