SAK-C505CA-4EMCA Infineon Technologies, SAK-C505CA-4EMCA Datasheet - Page 53

• Manufacturer Part Number: SAK-C505CA-4EMCA
• Description: IC, 8BIT MCU, 32K OTP, SMD
• Manufacturer: Infineon Technologies

Specifications of SAK-C505CA-4EMCA

• Core Size: 8bit
• No. Of I/o's: 34
• Program Memory Size: 32KB
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• Oscillator Type: External, Internal
• No. Of Timers: 3
• No. Of Pwm Channels: 4
• Digital Ic Case Style: MQFP
• Controller Family/series: C500
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Saving Modes
The C505 provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate
in normal operating mode and it can be also used for further power reduction in idle mode.
In the power down mode of operation,
be ensured, however, that
is restored to its normal operating level, before the power down mode is terminated.
a general overview of the entry and exit procedures of the power saving modes.
Table 10
Power Saving Modes Overview
Mode
Idle Mode
Power Down Mode
Slow Down Mode
Data Sheet
– Idle mode
– Power down mode
– Slow down mode
In the idle mode the main oscillator of the C505 continues to run, but the CPU is gated off from
the clock signal. All peripheral units are further provided with the clock. The CPU status is
preserved in its entirety. The idle mode can be terminated by any enabled interrupt of a
peripheral unit or by a hardware reset.
The operation of the C505 is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. Power down
mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/
INT0.or P4.1/RXDC.
The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency
significantly reduces power consumption.
ORL PCON, #01H
Entering
(Instruction
Example)
ORL PCON, #20H
ORL PCON, #02H
ORL PCON, #40H
ORL PCON,#10H
V
DD
is not reduced before the power down mode is invoked, and that
V
DD
can be reduced to minimize power consumption. It must
Leaving by
Ocurrence of an
interrupt from a
peripheral unit
Hardware Reset
Hardware Reset
Short low pulse at
pin P3.2/INT0 or
P4.1/RXDC
ANL PCON,#0EFH
or
Hardware Reset
49
C505/C505C/C505A/C505CA
Remarks
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
Oscillator frequency is
reduced to 1/32 of its nominal
frequency
Table 10
12.00
gives
V
DD