CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet
CS5501-BS
Specifications of CS5501-BS
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CS5501-BS Summary of contents
Page 1
... The converters’ low- pass, 6-pole Gaussian response filter is designed to al- low corner frequency settings from 0 the CS5501 and 0 the CS5503. Thus, each converter rejects 50 Hz and 60 Hz line frequencies as well as any noise at spurious frequencies. The CS5501 and CS5503 include on-chip self-calibra- ...
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... Notes: 1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the master clock frequency. Both source resistance and shunt capacitance are therefore critical in determining the CS5501’s source impedance requirements. For more information refer the text section Analog Input Impedance Considerations . ...
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... Unipolar Mode LSB’s %FS ppm Fs LSB’s 0.13 0.26 0.50 1.00 2.00 CS5503 Unit Conversion Factors, VREF = 2.5V CS5501/CS5503 VA+, VD+ = 5V; MIN MAX = 750 source CS5503-S, T Max Min Typ Max -55 to +125 0.003 - - 0.003 0.0015 - 0.0007 TBD 0.0012 ...
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... For Unipolar mode, Input Span is the difference between full scale and zero scale. For Bipolar mode, Input Span is the difference between positive and negative full scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of (VREF + 0.1). Specifications are subject to change without notice. 4 (Continued) CS5501/3- Min Typ - 2 - ...
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... CLKIN = 1 MHz 10 100 Frequency in Hz Frequency Response 1,2 S 3,4 S 5,6 -j1 - 0.241x + 0.0557x + 0.009664x , f = CLKIN/409,600, and f is the frequency of interest. -3dB -3dB CS5501/CS5503 Ratio CLKIN/ 256 CLKIN /1024 CLKIN /409,600 506,880/CLKIN 1000 = -1.4667 j1.8199 = -1.7559 j1.0008 = -1.8746 j0.32276 -1/2 + 0.00134x + 0.000155x ] Units ...
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... Symbol Min (Note 9) V (VD+)-1. out Symbol Min VD+ -0.3 VD- 0.3 VA+ -0.3 VA- 0 (VA-)-0.3 INA V -0.3 IND T - -65 stg CS5501/CS5503 10%; VA-, VD- = -5V 10%) Typ Max Units - - -40 A). OH out Max Units (VA+)+0.3 V -6.0 V 6 (VA+)+0.3 V (VA+)+0.3 V 125 C° ...
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... SLEEP High to CLKIN High (Note 17) Hold Time: SC1, SC2 hold after CAL falls Notes: 14. CLKIN must be supplied whenever the CS5501 or CS5503 is not in SLEEP mode clock is present when not in SLEEP mode, the device can draw higher current than specified and possibly become uncalibrated. ...
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... CLKIN t sls SLEEP Sleep Mode Timing for Synchronization CS5501/CS5503 ; VA+, VD 10%; Typ Max Units - - ns 25 100 ns 380 - ns 240 300 ns 730 790 1/CLKIN 1/CLKIN ns + 100 + 200 - 4/CLKIN ns +200 - 4.2 MHz ...
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... Hi-Z SCLK ( csd2 SDATA Hi-Z SCLK (i) DS31F2 MSB MSB-1 MSB-2 t dd1 t ph1 t pl1 SSC MODE Timing Relationships MSB MSB dd2 dd2 t ph2 MSB MSB-1 t dd2 t ph2 SEC MODE Timing Relationships CS5501/CS5503 LSB Hi-Z t fd2 Hi-Z t fd3 Hi-Z t pl2 LSB Hi-Z t fd4 9 ...
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... SWITCHING CHARACTERISTICS VA+, VD 10%; VA-, VD- = -5V Parameter AC Mode (Mode = VD-) CS5501 only Serial Clock (In) Serial Clock (In) Pulse Width High Pulse Width Low Set-up Time CS Low to SCLK Falling Maximum Data Delay Time SCLK Fall to New SDATA bit Output Float Delay CS High to Output Hi-Z (Note 21) Notes: 21 ...
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... S/H Amp Comparator DAC Figure 1. Charge Balance (Delta-Sigma) A/D Converter The analog modulator of the CS5501/CS5503 is a multi-order delta-sigma modulator. The modulator consists of a 1-bit A/D converter (that is, a com- parator) embedded in an analog feedback loop with high open loop gain (see Figure 1). The modulator samples and converts the input at a rate well above the bandwidth of interest ...
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... OVERVIEW As shown in the block diagram on the front page of the data sheet, the CS5501/CS5503 can be seg- mented into five circuit functions. The heart of the chip is the charge balance A/D converter (16-bit for the CS5501, 20-bit for the CS5503). The con- ...
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... This is be- cause the device is built using dynamic logic. Serial Interface Logic The CS5501 serial data output can operate in any one of the following three different serial interface modes depending upon the MODE pin selection: SSC (Synchronous Self-Clocking) mode; ...
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... Upon completion of transmission of all the data bits, the SCLK and SDATA outputs will high impedance state even with CS held low. In the event that CS is taken high before all data bits are output, the SDATA and SCLK outputs will CS5501/CS5503 Digital Time1 (LSB ...
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... DRDY returns high for four clock cycles. After this DRDY will fall and the port will be updated with a new 16-bit word in the CS5501 or 20-bit word in the CS5503 acceptable to clock out less than all possible data bits returned high to allow the port to be updated ...
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... Some serial data rates can be quite slow compared to the rate at which the CS5501 can up- date its output port. A slow data rate will leave only a short period of time to start the second 11- bit packet returned high momentarily ...
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... To assure that the CS5501/CS5503 achieves excellent performance over time and temperature, it uses digital calibration techniques to minimize offset and gain errors to typically within 1/2 LSB at 16 bits in the CS5501 and 4 LSB at 20 bits in the CS5503. Converter Calibration The CS5501/CS5503 offer both self-calibration and system level calibration capability ...
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... DRDY remains high throughout the calibration sequence. In Self-Cal mode (SC1 and SC2 low) DRDY falls once the CS5501 or CS5503 has settled to the analog input. In all other modes DRDY falls immediately after the calibration term has been determined. 18 Figure 9). System calibration performs the same ...
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... V before an endpoint of the transfer function exceeds the input overrange limit. Initiating Calibration Table 2 illustrates the calibration modes available in the CS5501/CS5503. Not shown in the table is the function of the BP/UP pin which determines whether the converter is calibrated to measure bi- polar or unipolar signals. A calibration step is ...
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... AGND + 0.5 LSB <(SOFF + 0.5 LSB) <(AGND+0.5 LSB) Tables 3 and 4 indicate the output code size and output coding of the CS5501/CS5503 in its vari- ous modes. The calibration equations which represent the CS5501/CS5503 transfer function are shown in Figure 10. DOUT = Slope (AIN - Unipolar Offset) + 0.5 LSB a ...
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... CS501X Series of A/D Converters" for further discussion on the clamp diode input structure and on current limiting circuits. System Synchronization If more than one CS5501/CS5503 is included in a system which is operating from a common clock, all of the devices can be synchronized to sample and output at exactly the same time. This can be accomplished in either of two ways ...
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... The typical gain drift over the specified -80 temperature range is less than 2.5 LSBs for the -160 CS5501 and less than 40 LSBs for the CS5503 . -240 Measurement errors due to offset drift or gain drift can be eliminated at any time by recalibrat- -320 ing the converter ...
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... Filtering At the system level, the digital filter in the CS5501/CS5503 can be modeled exactly like an analog filter with a few minor differences. Digital filtering resides behind the A/D conver- sion and can thus reject noise injected during the conversion process (i.e. power supply rip- ple, voltage reference noise, or noise in the ADC itself) ...
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... Table 5. Settling Time of the 6 Pole Low Pass Filter in the CS5501 to 1/2 LSB Accuracy with a Full Scale Step Input 24 Post Filtering Post filtering is useful to enhance the noise per- formance of the CS5503. With a constant input voltage the output codes from the CS5503 will exhibit some variation due to noise ...
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... This specification assumes a clean reference voltage. DS31F2 band-gap references are available which can sup- ply 2.5 V for use with the CS5501/CS5503. Many of these devices are not specified for noise, especially in the 0 bandwidth. Some of these devices may exhibit noise characteristics which degrade the performance of the CS5501/CS5503 ...
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... If sepa- rate supplies are used recommended that the CS5501/CS5503 be powered up first com- mon power source is used for the analog signal conditioning circuitry as well as the A/D con- verter, this power source should be applied before application of power to the digital logic supply ...
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... CS5501/CS5503 reading will occur after a rising edge on SLEEP occurs. Battery Backed-Up Calibrations The CS5501/CS5503 use SRAM to store calibra- tion information. The contents of the SRAM will be lost whenever power is removed from the chip. Figure 17 shows a battery back-up scheme that can be used to retain the calibration memory dur- ing system down time and/or protect it against intermittent power loss ...
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... V supply drops slowly during power-down. As the supply drops below the battery voltage but not yet below the logic threshold of the SLEEP pin, the battery will be supplying the CS5501/CS5503 at full power (typically 3 mA). Faster transitions at SLEEP can be triggered using a resistive di- vider or a simple resistor network to generate the SLEEP input from the +5 V supply ...
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... Serial Output I/O MODE -Serial Interface Mode Select, Pin 1. Selects the operating mode of the serial port. If tied to VD- (-5V), the CS5501 will operate in the UART-compatible AC mode for Asynchronous Communication. The SCLK pin will operate as an input to set the data rate, and data will transmit formatted with one start and two stop bits ...
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... BP/UP is changed. CAL -Calibrate, Pin 13. If brought high for 4 clock cycles or more, the CS5501/CS5503 will reset and upon returning low a full calibration cycle will begin. The state of SC1, SC2, and BP/UP when CAL is brought low determines the type and length of calibration cycle initiated (see Table 2). Also, a single CAL signal can be used to strobe the CAL pins high on several CS5501/CS5503’ ...
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... VD- -Negative Digital Power, Pin 6. Negative digital supply voltage. Nominally -5 volts. DGND -Digital Ground, Pin 5. Digital ground. VA+ -Positive Analog Power, Pin 14. Positive analog supply voltage. Nominally +5 volts. VA- -Negative Analog Power, Pin 7. Negative analog supply voltage. Nominally -5 volts. AGND -Analog Ground, Pin 8. Analog ground. DS31F2 CS5501/CS5503 31 ...
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... Units in volts. Offset Calibration Range The CS5501/CS5503 calibrate their offset to the voltage applied to the AIN pin when in system calibration mode. The first code transition defines Unipolar Offset when BP/UP is low and the mid-scale transition defines Bipolar Offset when BP/UP is high. The Offset Calibration Range specification indicates the range of voltages applied to AIN that the CS5501 or CS5503 can accept and still calibrate offset accurately ...
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... Ordering Guide Model Number No. of Bits CS5501-AS 16 CS5501-BS 16 CS5501-AP 16 CS5501-BP 16 CS5501-CP 16 CS5501-SD 16 CS5501-TD 16 CS5503-AS 20 CS5503-BS 20 CS5503-AP 20 CS5503-BP 20 CS5503-CP 20 CS5503-SD 20 CS5503-TD 20 DS31F2 Linearity Error (Max) Temperature Range 0.003% -40 to +85 C 0.0015% -40 to +85 C 0.003% -40 to +85 C 0.0015% -40 to +85 C 0.0012% -40 to +85 C 0.003% -55 to +125 C 0 ...
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... DRDY pin can be polled for a rising transition directly can be latched as a level- sensitive interrupt. With the CS input tied low the CS5501 will shift out every available sample (4kHz word rate with a 4MHz master clock). Lower output rates (and interrupt rates) can be generated by dividing down the DRDY output and applying ...
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... CS5501 into a known state. For each interface, a second subroutine is also provided which will collect one complete 16-bit output word from the CS5501. Figure A5 illus- trates the detailed timing throughout the subroutine for one particular interface - the COPS family interface of Figure A4. ...
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... Put most significant byte in A STAA SPDR ; Start serial port for second byte ; Get port status BPL WAIT2 ; If SPIF (MSB data yet, wait LDAB #%x1xxxxxx ; STAB PORTA ; inactive; deselect CS5501 LDAB SPDR ; Put least significant byte in B RTS ; inactive; deselect CS5501 RC ; Reset carry, used in next XAS ...
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... Shift in HI-Z B15 (MSB) GETLP: JP GETLP: NOP XAS XIS GETLP A SIO skip JP XIS GETLP RC XAS SIO HI-Z Figure A5. Serial Timing Example - COPS CS5501/CS5503 GETLP: NOP NOP NOP XAS XIS A SIO B14 B13 B12 B11 JP GETLP: NOP XAS XIS GETLP NOP A SIO ...
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... PSW ; Restore original value ; Set SMOD = 1, baud = OSC/ inactive SCON,#1001000B ; Enable serial port mode 2, ; receiver enabled, transmitter disabled ES ; Disable serial port interrupts (polling active; select CS5501 RI,$ ; Wait for first byte RI ; A,SBUF ; Put most significant byte in A RI,$ ; wait for second byte RI ; ...
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... CS5501 CS SCLK MODE SDATA -5V Figure A8. TMS70X2/CS5501 Serial Interface Notes: 1. CS5501 in Asynchronous (UART-like) mode. 2. TMS70X2 in Isosynchronous mode. 3. TMS70X2 with 8 MHz master clock has max baud =1.0 Mbps. Assumptions used as CS. 2. Receive data via polling. 3. Word received put in A and B upon return byte. ...
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Notes • ...
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... The evaluation board interfaces with most microcontrol- lers and allows full control of the features of the CS5501 or CS5503. DIP switch selectable control is also avail- able in the event a microcontroller is not used. The evaluation board also offers computer data interfaces in- cluding RS-232 and parallel port outputs for evaluating the CS5501 ...
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... CS to read the data at a much lower rate. A decimation counter is provided on the board for this purpose. The counter reduces the rate at which the CS line of the CS5501 is activated by only allowing CS to occur at a sub-multiple of the DRDY rate. Parallel Output Port (for CS5501 only) The output data from the CS5501/CS5503 is in serial form ...
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... RS-232 Port (for CS5501 only) The CS5501 has a data output mode in which it formats the data to be UART compatible; each serial output byte is preceded by a start bit and terminated with two stop bits. Serial data in this format is commonly transferred using the RS-232 data interface ...
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... CLKOUT Y2 3 CLKIN CLKIN (fig. 1) *AC Mode available only in CS5501 44 Connector P1 allows jumper selection of either an external clock or the on-board 4.9152 MHz crys- tal oscillator (See Figure 1 for schematic) as the clock source for the CLKIN signal on pin 3 of the CS5501/CS5503 (shown in Figure 2). ...
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... DRDY pin (pin 18 output from the chip which signals whenever a new data word is avail- able in the internal output register of the CS5501/CS5503. Data can then be read from the register, but only when the CS pin (pin 16) is low. When CS is low, data bits are output in serial form on the SDATA pin (pin 20) ...
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... Be aware that an arbitrarily timed DACK signal may cause the output data regis- ters to be enabled in the middle of an output word if the CS signal to the CS5501 is not properly sequenced. This will result in incorrect data in the output registers. If the Decimation Counter is used to control the ...
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SCLK (fig. 2) SDATA (fig C22 0 U8A 74HC74 3 CL DCS (fig DS31DB3 Vcc C14 0 Vcc U10 PH 74HCT299 RST ...
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... NC (no connection) position to allow the micro- controller full control over the signals on P10. AC (Asynchronous Communication) Mode (for CS5501 evaluation only) The AC mode enables the CS5501 to output data in a UART-compatible format. Data is output as two characters consisting of one start bit, eight data bits, and two stop bits each. ...
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... Figure 2). The outputs of the counter are available at connector P4. The counter accumulates 2n+1 counts ( which time the selected output enables the CS input to the CS5501/CS5503 (if the jumper the DC, Decimation Counter, position). The CDB5501/CDB5503 n+1 DRDY Pulses Before CS is ...
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... The analog signal input range in the bipolar mode is set by the reference to be from +VREF to - VREF. If the input signal goes above +VREF, the SLP CAL CS5501/CS5503 will output all "1’s". Input sig- nals below -VREF cause the output data to be all "0’s". CDB5501/CDB5503 Cal Type ...
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... VIN VOUT 6 C16 U5 R8 LT1019-2 0 TRIM GND CW 4 TP15 C21 0.0047 F X7R R16 200 AIN Figure 6. Voltage Reference / Analog Input CDB5501/CDB5503 the analog input of the chip 14 VA+ CS5501/ R6 CS5503 DGND 0 VREF C19 10 F R10 2.4 8 AGND 9 AIN 0.1 F 0.1 F ...
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... DRDY to trigger). With proper horizontal sweep, the SDATA output bits from the A/D converter can be observed. Note that if the input voltage to the CS5501 is adjusted to a mid-code value, the converter will remain stable on the same output code. This illus- trates the low noise level of the CS5501. The CS5503 will exhibit a few LSB’ ...
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DS31DB3 Figure 7. CDB5501/CDB5503 Component Layout CDB5501/CDB5503 53 ...
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