CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 8

• Manufacturer Part Number: CS5501-BS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5501-BS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SWITCHING CHARACTERISTICS
VA-, VD- = -5V
Notes: 18. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete
8
SC1, SC2
SSC Mode (Mode = VD+)
Access Time
SDATA Delay Time
SCLK Delay Time
(at 4.096 MHz)
Serial Clock
(Out)
Output Float Delay
Output Float Delay
SEC Mode (Mode = DGND)
Serial Clock (In)
Serial Clock (In)
Access Time
Maximum Data Delay Time
Output Float Delay
Output Float Delay
Calibration Control Timing
CAL
19. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
20. SDATA transitions on the falling edge of SCLK(i).
the current data bit and then go to high impedance.
for 4 clock cycles. The propagation delay time may be as great as 4 CLKIN cycles plus 160 ns.
To guarantee proper clocking of SDATA when using asychronous CS, SCLK(i) should not be taken
high sooner than 4 CLKIN cycles plus 160ns after CS goes low.
10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C
t
scs
VALID
Parameter
t
sch
CS Low to SDATA Out
SCLK Falling to New SDATA bit
SDATA MSB bit to SCLK Rising
Pulse Width High (at 4.096 MHz)
Pulse Width Low
SCLK Rising to Hi-Z
CS High to Output Hi-Z (Note 18)
Pulse Width High
Pulse Width Low
CS Low to Data Valid
SCLK Falling to New SDATA bit
CS High to Output Hi-Z
SCLK Falling to Output Hi-Z
SLEEP
CLKIN
(continued) (T
Sleep Mode Timing for
(Note 19)
(Note 20)
Synchronization
Symbol
A
t
t
t
t
t
f
t
t
csd1
csd2
t
t
t
t
t
t
sclk
dd1
cd1
ph1
ph2
dd2
fd2
fd1
fd3
fd4
pl1
pl2
= T
min
L
t
= 50 pF)
sls
3/CLKIN
to T
Min
250
180
dc
50
-
-
-
-
-
-
-
-
-
max
; VA+, VD+ = 5V
1/CLKIN
+ 100
CS5501/CS5503
Typ
380
240
730
100
25
80
75
-
-
-
-
-
-
SDATA
SSC Mode (Note 19)
Output Float Delay
CS
1/CLKIN
4/CLKIN
+ 200
+200
Max
100
300
790
160
150
250
200
4.2
-
-
-
-
10%;
DS31F2
Units
MHz
t
fd1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns