CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 34

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CS5501-BS

Manufacturer Part Number
CS5501-BS
Description
A/D Converter (A-D) IC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS5501-BS

Peak Reflow Compatible (260 C)
No
No. Of Bits
16 Bit
Leaded Process Compatible
No
Mounting Type
Surface Mount
Interface Type
Serial
Package / Case
20-SOIC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
CS5501-BS
Manufacturer:
CIRRUS
Quantity:
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Part Number:
CS5501-BSZ
Manufacturer:
CIRRUS
Quantity:
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APPENDIX A: APPLICATIONS
Parallel Interface
Figures A1 and A2 show two serial-to-parallel
conversion circuits for interfacing the CS5501 in
its SSC mode to 16- and 8-bit systems respec-
tively. Each circuit includes an optional
74HCT74 flip-flop to latch DRDY and generate
a level-sensitive interrupt.
Both circuits require that the parallel read process
be synchronized to the CS5501’s operation. That
is, the system must not try to enable the regis-
ters’ parallel output while they are accepting
serial data from the CS5501. The CS5501’s
DRDY falls just prior to serial data transmission
34
+5V
MODE
CS
CS5503
CS5501
SDATA
DRDY
SCLK
+5V
+5V
A
S1
S2
Q
A
S1
S2
OE2 OE1
H
Figure A1. 16-bit Parallel Interface
OE1
OE2
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
and returns high as the last bit shifts out. There-
fore, the DRDY pin can be polled for a rising
transition directly, or it can be latched as a level-
sensitive interrupt.
With the CS input tied low the CS5501 will shift
out every available sample (4kHz word rate with
a 4MHz master clock). Lower output rates (and
interrupt rates) can be generated by dividing
down the DRDY output and applying it to CS.
Totally asynchronous interfaces can be created
using a Shift Data control signal from the system
which enables the CS5501’s CS input and/or the
shift registers’ S1 inputs. The DRDY output can
then be used to disable serial data transmission
once an output word has been fully registered.
D
RESET
SET
CS5501/CS5503
Only needed for
interrupt driven systems
Q
Q
(For polling)
CS
INT
DRDY
DS31F2

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