CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 18

• Manufacturer Part Number: CS5501-BS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5501-BS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

represents the gain slope for the input to output
transfer function of the converter. In unipolar
mode the calibration microcontroller determines
the slope factor by dividing the span between the
zero point and the full scale point by the total
resolution of the converter (2
resulting in 65,536 segments or 2
CS5503, resulting in 1,048,578 segments). In bi-
polar mode the calibration microcontroller divides
the span between the zero point and the full scale
point into 524,288 segments for the CS5503 and
32,768 segments for the CS5501. It then extends
the measurement range 524,288 segments for the
CS5503, 32,768 segments for the CS5501, below
the zero scale point to achieve bipolar measure-
ment capability. In either unipolar or bipolar
modes the calculated slope factor is saved and
later used to calculate the binary output code
when an analog signal is present at the AIN pin
during measurement conversions.
System calibration allows the A/D converter to
compensate for system gain and offset errors (see
18
* DRDY remains high throughout the calibration sequence. In Self-Cal mode (SC1 and SC2 low) DRDY
Transducer
falls once the CS5501 or CS5503 has settled to the analog input. In all other modes DRDY falls
immediately after the calibration term has been determined.
CAL
VREF sys
SC1
0
1
0
1
SC2
0
1
1
0
A0 A1
Analog
MUX
16
System Offset
System Offset
& System Gain
Cal Type
for the CS5501,
Self-Cal
20
Figure 9. System Calibration
Table 2. Calibration Control
for the
Conditioning
Circuitry
AGND
ZS Cal
Signal
AIN
AIN
-
Figure 9). System calibration performs the same
slope factor calculations as self cal but uses volt-
age values presented by the system to the AIN pin
for the zero scale point and for the full scale
point. Table 2 depicts the calibration modes
available. Two system calibration modes are
listed. The first mode offers system level calibra-
tion for system offset and for system gain. This is
a two step calibration. The zero scale point (sys-
tem offset) must be presented to the converter
first. The voltage that represents zero scale point
must be input to the converter before the calibra-
tion step is initiated and must remain stable until
the step is complete. The DRDY output from the
converter will signal when the step is complete by
going low. After the zero scale point is calibrated,
the voltage representing the full scale point is in-
put to the converter and the second calibration
step is initiated. Again the voltage must remain
stable throughout the calibration step.
This two step calibration mode offers another cali-
bration feature. After a two step calibration
VREF
VREF
FS Cal
AIN
-
CS5501
CS5503
CAL SC1 SC2
Sequence
One Step
One Step
2nd Step
1st Step
SDATA
SCLK
Calibration Time
CS5501/CS5503
3,145,655/f
1,052,599/f
1,068,813/f
2,117,389/f
CLK
DATA
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
clk
clk
clk
clk
C
DS31F2