CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 46

• Manufacturer Part Number: CS5501-BS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5501-BS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CS5501/CS5503 Data Output Mode Selection
Connector P5 (see Figure 2) allows jumper selec-
tion of any one of the three data output modes.
These modes are:
SSC (Synchronous Self-Clocking) Mode
The SSC mode is designed for interface to those
microcontrollers which allow external clocking of
their serial inputs. The SSC mode also allows
easy connection to serial-to-parallel conversion
circuitry.
In the SSC mode serial data and serial clock are
output from the CS5501/CS5503 whenever the
CS line is activated. As illustrated in Figure 2, all
of the signals are available at connector P10. If
the CS signal is to be controlled remotely the
jumper on P9 should be placed in the NC (No
Connection) position. This removes the Decima-
tion Counter output from controlling the CS line.
Data Output Interface: Parallel Port (for
CS5501 evaluation only).
Whenever the CS5501 is operated in the SSC
mode the 16-bit output data is clocked into two
8-bit shift registers. The registers have three-state
parallel outputs which are available at P7 (see
Figure 3). A flip-flop (U8A) is used to signal the
remote reading device whenever the registers are
updated. The PDR (Parallel Data Ready) signal
from the flip-flop is available on P7. The Q-bar
output from the flip-flop locks out any further up-
dates to the registers until their data is read and a
DACK (Data ACKnowledge) signal is received
from the remote device.
Activation of the CS line determines the rate at
which the CS5501 will attempt to update the out-
put shift registers. Data will be shifted into the
46
1) SSC (Synchronous Self-Clocking);
2) SEC (Synchronous External Clocking);
3) AC (Asynchronous Communication).
(AC mode is available only in the CS5501)
registers only if a DACK signal has occurred
since the last update.
The CS line can be controlled remotely at P10 or
by the output of the Decimation Counter. If CS is
controlled remotely, the Decimation divide
jumper on P4 should be placed in the "0" posi-
tion. This insures that the DCS signal will occur
at the same rate CS is activated. The positive go-
ing edge of DCS toggles the U8A flip-flop which
signals an update to the parallel port.
The parallel registers are set up to be read in 16-
bit parallel fashion but can be configured to be
read separately as two 8-bit bytes on an 8-bit bus.
To configure the board for byte-wide reads, the
byte-wide jumpers must be soldered in place. In
addition, for proper "one byte at a time" address
selection, a connection on the circuit board needs
to be opened and a jumper wire soldered in the
proper place to determine which register is to be
read when A0 is a "1" and vice versa. See Figure
3 for schematic details. The evaluation board
component layout diagram, Figure 7, indicates the
location of the byte-wide jumpers and A0 address
selection jumpers.
After data is read from the registers a DACK
(Data Acknowledge) signal is required from the
off-board controller to reset flip-flop U8A. This
enables the registers to accept data input once
again.
The DRB and CSB signals on connector P10
should be used to monitor and control the
CS5501 output to the serial to parallel conversion
registers. Be aware that an arbitrarily timed
DACK signal may cause the output data regis-
ters to be enabled in the middle of an output
word if the CS signal to the CS5501 is not
properly sequenced. This will result in incorrect
data in the output registers.
If the Decimation Counter is used to control the
output of the CS5501 (Jumper on P9 in the DC
position), the CSB signal on P10 can be moni-
CDB5501/CDB5503
DS31DB3