CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 43

• Manufacturer Part Number: CS5501-BS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5501-BS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RS-232 Port (for CS5501 only)
The CS5501 has a data output mode in which it
formats the data to be UART compatible; each
serial output byte is preceded by a start bit and
terminated with two stop bits. Serial data in this
format is commonly transferred using the RS-232
data interface. Therefore the evaluation board in-
cludes an RS-232 driver and output connector.
The CS5503 does not provide this output mode.
Micro Port
The CS5501/CS5503 was designed to be compat-
ible with many micro-controllers. Therefore the
evaluation board provides access to all of the data
output pins and the control pins of the
CS5501/CS5503 on header connectors.
DIP Switch and CAL Pushbutton
Although all of the control lines to the
CS5501/CS5503 are available on header connec-
tors at the edge of the board, it is preferable to not
require software control of all of these pins.
Therefore DIP switch control is provided on some
of these control lines. The CAL input to the
CS5501/CS5503 is made available at a header pin
for remote control, but pushbutton control of CAL
is also provided.
DS31DB3
CLKIN
4.9152 MHz
C1
30 pF
1
2
10 M
U1A
R1
Y1
TP2
3
R2
5.1 k
200
R3
C2
30 pF
74HC00
5
4
U1B
6
TP1
EXTCLK
INTCLK
P1
13
10
12
9
Figure 1. Clock Generator
U1C
U1D
V+
14
7
11
8
C3
0.1 F
TP3
N = 0
P11 Connects the baud clock from the on-board
Jumper Selections
The evaluation board has many jumper selectable
options. This table describes the jumper selections
available.
11
10
P2
P1 Selects between the on-board 4.9152 MHz
P2 Allows any of the counter/divider output
P3 Allows selection of baud rate clocks when
P4 Selects the divide ratio of the Decimation
P5 Selects one of the three available output data
P9 Enables the output of the Decimation
CL
R
1
9
1
TP4
oscillator (INT) or an external (EXT) clock
source as the input to the clock generator/
divider chain.
clock rates to be selected as the input clock
to the CS5501/CS5503.
the CS5501 is in the UART compatible mode.
When using the on-board 4.9152 MHz stand-
ard baud rates between 1200 and 19,200 are
available.
Counter.
modes of the CS5501 or one of two available
output data modes of the CS5503.
Counter to control the CS line of the
CS5501/CS5503.
clock divider as the input to the SCLK pin
of the CS5501/CS5503.
2
7
2
Master Clock
3
6
3
4
5
4
5
3
5
74HC4040
6
2
6
U2
TP5
7
4
7
8
CDB5501/CDB5503
13 12 14 15 1
8
9 10 11 12
9 10 11 12
Baud Clock
P3
16
8
BRCLK (fig. 2)
CLKIN (fig. 2)
V+
C5
0.1 F
43