EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 344
![IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC](/photos/12/23/122386/ep9307-cr_sml.jpg)
EP9307-CR
Manufacturer Part Number
EP9307-CR
Description
IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9307-CR
Rohs Compliant
NO
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1254
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-CR
Manufacturer:
CIRRUSL
Quantity:
5
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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- Download datasheet (13Mb)
9
9-42
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
Chip Reset:
Rx Reset:
Soft Reset:
Definition:
Bit Descriptions:
Note: The IA field of the table means the same Individual Addresses as RxFCE, that is, IA0
implies RxFCE0 and IA1 implies RxFCE1
Individu
Accept
IA[1:0]
al
0
1
1
1
Table 9-4. Individual Accept, RxFlow Control Enable and Pause Accept Bits
0x0000_0x0x
0x0000_0000
0x0000_0000
Receiver Control Register. The Receive Control register is reset by Rx Reset
signal generated by holding the TESTSELn pin low. The same signal is also
used to reset the receive MAC. The purpose of having a separate reset signal
is to be able to avoid resetting the receive MAC when the AHB bus is in a
powered down state (RESET active), and wake-up frames need to be
detected.
RSVD:
PauseA:
RxFCE[1:
Receive
Control
Enable
Flow
0]
X
1
1
0
Copyright 2007 Cirrus Logic
PauseA
Accept
Pause
X
X
0
1
Reserved. Unknown During Read.
Pause Accept. When set, Pause frames are passed on to
the Host as regular frames. When clear, the frames are
discarded. The handling of MAC Control frames depends
on the Pause Accept bit as well as the appropriate
Individual Accept and RxFlow Control Enable bits, as
follows.
Frame discarded (do not pass the address filter)
MAC Control frames are recognized, flow control action taken,
and frames not passed to host. Non pause MAC Control
frames are passed on to host.
MAC Control frames are recognized, flow control action taken,
and all MAC control frames are passed on to host.
MAC Control frames are not distinguished from other frame
types, all frames passed on to host.
Action
DS785UM1
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