EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 701

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

DS785UM1
AC97RISRx
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
TXBUSY:
TXFF:
RXFF:
TXFE:
RXFE:
AC97RISR1 - 0x8088_0010 - Read Only
AC97RISR2 - 0x8088_0030 - Read Only
AC97RISR3 - 0x8088_0050 - Read Only
AC97RISR4 - 0x8088_0070 - Read Only
Raw Interrupt Status. The AC97ISR registers are the raw Interrupt status
registers for the controller FIFOs. All bits are cleared to zero on reset except
for the TCIS as the FIFO and shift register should both be empty. Any write to
this register clears the overrun error.
RSVD:
RIS:
TIS:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
TXBUSY is set when TEN = “1” AND there is data in the
FIFO, OR when data from this FIFO is being sent in the
current frame.
TXBUSY is cleared at the start of the next frame following
the assertion of the corresponding channel’s TXFE flag
(the value of TEN is irrelevant).
Transmit FIFO full flag, active HIGH.
This bit is asserted HIGH if the transmit FIFO is full.
Receive FIFO full flag, active HIGH.
This bit is asserted HIGH if the receive FIFO is full.
Transmit FIFO empty flag, active HIGH.
This bit is asserted HIGH if the transmit FIFO is empty.
Receive FIFO empty flag, active HIGH.
This bit is asserted HIGH if the receive FIFO is empty.
Reserved. Unknown During Read.
RX Interrupt Status - This bit is set to “1” if the receive
FIFO becomes half full.
TX Interrupt Status - This bit is set to “1” if the transmit
FIFO becomes half empty.
24
8
RSVD
23
7
22
6
21
5
20
4
RIS
19
3
EP93xx User’s Guide
TIS
18
2
AC’97 Controller
RTIS
17
1
22-13
TCIS
16
0
22