EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 385

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

TXStsQBLen
DS785UM1
31
15
Soft Reset:
Definition:
Bit Descriptions:
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x0000_0000
Unchanged
Transmit Status Queue Base Address. The Transmit Status Queue Base
Address defines the system memory address of the transmit status queue.
This address is used by the MAC to reload the Transmit Current Status
Address whenever the end of the status queue is reached. The base address
should be set at initialization time and must be set to a word aligned memory
address.
TSQBA:
0x8001_00C4 - Read/Write
0x0000_0000
Unchanged
Transmit Status Queue Base Length. The Transmit Status Queue Base
Length defines the actual number of bytes in the transmit status queue. The
length should be set at initialization time and must define an integral number
of transmit statuses.
RSVD:
TSQBL:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Transmit Status Queue Base Address.
Reserved. Unknown During Read.
Transmit Status Queue Base Length.
24
8
TSQBL
RSVD
23
7
22
6
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
19
3
EP93xx User’s Guide
18
2
17
1
16
9-83
0
9