EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 730

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

23
SSPCPSR
SSPIIR / SSPICR
23-18
Synchronous Serial Port
EP93xx User’s Guide
31
15
31
15
Address:
Default:
Definition:
Bit Descriptions:
Address:
Default:
Note: A write to this register clears the receive overrun interrupt, regardless of the data value
30
14
30
14
written.
29
13
29
13
28
12
28
12
0x808A_0010 - Read/Write
0x0000_0000
SSPCPSR is the clock prescale register and specifies the division factor by
which the input SSPCLK should be internally divided before further use.
The value programmed into this register should be an even number between 2
and 254. The least significant bit of the programmed number is hard-coded to
zero. If an odd number is written to this register, data read back from this
register will have the least significant bit as zero.
RSVD:
CPSDVSR:
0x808A_0014 - Read Only
0x0000_0000
RSVD
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
RSVD
25
25
9
9
Reserved. Unknown During Read.
Clock pre-scale divisor. Should be an even number from 2
to 254, depending on the frequency of SSPCLK. The least
significant bit CPSDVSR[0] always returns zero on reads
since it is hard-coded to 0
24
24
8
8
RSVD
RSVD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
CPSDVSR
19
19
3
3
RORIS
18
18
2
2
TIS
17
17
1
1
DS785UM1
RIS
16
16
0
0