CDB42438 Cirrus Logic Inc, CDB42438 Datasheet - Page 22

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CDB42438

Manufacturer Part Number
CDB42438
Description
Eval Bd 108dB 6&8ch Multi-Chnl CODECs
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB42438

Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS42438
Primary Attributes
6 Single-Ended and 2 Differential Analog Inputs and 8 Outputs, S/PDIF Transmitter and Receiver
Secondary Attributes
Graphic User Interface
Description/function
Audio CODECs
Operating Supply Voltage
5 V to 12 V
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS42438
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
Other names
598-1500
5.8
22
Reserved
7
CS5341 AND MISCELLANEOUS CONTROL (ADDRESS 08H)
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
Default = 0
0 - Disabled
1 - Enabled
Function:
Default = 0
0 - Divide by 1.5
1 - Divide by 2.0
Function:
Default = 0
0 - Disabled
1 - Enabled
Function:
Default = 0
0 - Divide by 1.5
1 - Divide by 2.0
Function:
Default = 0
0 - Left Justified
1 - I
²
Enables/disables the internal (1.5 or 2.0) divide circuitry for MCLK.
Divides the internal MCLK by 1.5 or 2 to all internal logic. This is intended to accommodate an external
MCLK that is greater than 256 Fs. SCLK is derived from MCLK and must always be 256Fs in TDM
Mode (see Figure 6 on page 13).
Enables/disables the internal (1.5 or 2.0) divide circuitry for the CS5341 MCLK.
Divides the MCLK from the MCLK bus to the CS5341 by 1.5 or 2 (see Figure 6 on page 13).
S
Reserved
INT MCLK DIVIDE (1.5/2.0 DIVIDE)
EXT MCLK DIVIDE (‘41_MCLK_DIV)
1.5 OR 2.0 CS5341 MCLK DIVIDE (‘41_DIV_1.5/2.0)
1.5 OR 2.0 MCLK DIVIDE (1.5/2.0 DIVIDE)
LEFT-JUSTIFIED OR I
6
INT.MCLK_
DIV
5
²
S INTERFACE FORMAT (‘41_I
INT.DIV_
1.5/2
4
‘41_MCLK_
DIV
3
²
‘41_DIV_
S/LJ)
1.5/2
2
‘41_I²S/LJ
1
CDB42438
DS646DB2
‘41_RST
0

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