CDB42438 Cirrus Logic Inc, CDB42438 Datasheet - Page 9

• Manufacturer Part Number: CDB42438
• Description: Eval Bd 108dB 6&8ch Multi-Chnl CODECs
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42438

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42438
• Primary Attributes: 6 Single-Ended and 2 Differential Analog Inputs and 8 Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V to 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42438
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1500

3. FPGA SYSTEM OVERVIEW
The FPGA (U16) controls all digital signal routing between the CS42438, CS8406 CS8416,
CS5341 and the DSP I/O Header. For easy evaluation of the TDM interface format of the
CS42438, the FPGA will copy stereo PCM data from either the CS8416 or DSP I/O Header onto
one data line at a 256Fs data rate. It will in turn de-multiplex the TDM data from the CS42438
and output stereo channel pairs to the CS8406.
DS646DB2
3.1
Sections 3.2 to 3.4 show graphical descriptions of the routing topology internal to the FPGA.
Section 3.5 shows the graphical description of the FPGA’s control of the MCLK bus. And sec-
tion 3.6 provides details for routing clocks and data, bypassing the FPGA (recommended for
more advanced users only). Refer to “FPGA Register Description” on page 16 for all config-
uration settings.
The board may also be configured simply by choosing from 6 pre-defined scripts provided in
the supplied CD ROM. The pre-defined scripts, along with a brief description, are shown be-
low.
This script sets up the CDB42438 to operate the CS8416 as the master and all other de-
vices as slave. The CS8416 masters the MCLK bus.
Various permutations of this option exist as S/PDIF1, S/PDIF2, S/PDIF3 and S/PDIF4.
Each permutation signifies which ADC data is transmitted to the CS8406.
The CS42438 operates in the TDM digital interface format. The FPGA copies PCM data
from the CS8416 onto one data line and transmits this data to the DAC_SDIN input.
This script sets up the CDB42438 to operate the crystal oscillator as the master. The
CS8416 passes the signal from the crystal oscillator, Y1, through its OMCK input and out
its RMCK output (NOTE: the S/PDIF input must be disconnected). The CS8416 then gen-
erates sub clocks derived from the crystal oscillator and input to the FPGA for TDM clock
generation. The FPGA then masters the sub clocks to the CS42438.
The CS42438 operates in the TDM digital interface format, looping ADC_SDOUT back
into the DAC_SDIN input. ADC1-3 appear on DAC1-3 and the CS5341 ADC appears on
DAC4.
This script sets up the CDB42438 to operate the device attached to the DSP Header as
the master and all other devices as slave. The DSP Header masters the MCLK bus.
3.1.1
3.1.2
3.1.3
FPGA Setup
S/PDIF In, S/PDIF Out (SPDIF1-4)
Analog In, Analog Out (Digital Loopback)
DSP Routing
CDB42438
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