CDB42438 Cirrus Logic Inc, CDB42438 Datasheet - Page 19

• Manufacturer Part Number: CDB42438
• Description: Eval Bd 108dB 6&8ch Multi-Chnl CODECs
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42438

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42438
• Primary Attributes: 6 Single-Ended and 2 Differential Analog Inputs and 8 Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V to 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42438
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1500

5.6
NOTE: To avoid contention with the FPGA, set the clock direction for the FPGA appropriately: FPGA->CODEC in
register 03h must be set to ‘1’b.
DS646DB2
BypassFPGA
7
BYPASS CONTROL (ADDRESS 06H)
5.5.3
5.5.4
5.5.5
5.6.1
Default = 0
0 - 256 Fs
1 - 128 Fs
Function:
Default = 0
0 - Left-Justified
1 - I
Function:
Default = 0
0 - Enabled
1 - Disabled
Function:
Default = 1
0 - Enable
1 - Disable
Function:
²
is held low for 300 µs whenever this bit changes.
Selects the RMCK/LRCK ratio for the CS8416. Pin 6 (RST bit) is held low for 300 µs whenever this
bit changes.
Selects either I
µs whenever this bit changes.
Enables/disables the external MCLK output buffer on the MCLK bus (see Figure 6 on page 13).
This bit toggles a control line for the external data buffer to route the DSP directly to the CODEC.
S
DSPDATA
RMCK/LRCK RATIO SELECT (128/256 FS)
LEFT-JUSTIFIED OR I
RMCK MASTERS MCLK BUS (RMCK_MASTER)
BYPASS FPGA (BYPASSFPGA)
->DAC
6
²
S or Left Justified interface format for the CS8416. Pin 6 (RST bit) is held low for 300
Reserved
5
²
S INTERFACE FORMAT (I
CS5341
->AUX
4
Reserved
3
²
S/LJ)
Reserved
2
Reserved
1
CDB42438
Reserved
0
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