CDB42438 Cirrus Logic Inc, CDB42438 Datasheet - Page 3

• Manufacturer Part Number: CDB42438
• Description: Eval Bd 108dB 6&8ch Multi-Chnl CODECs
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42438

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42438
• Primary Attributes: 6 Single-Ended and 2 Differential Analog Inputs and 8 Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V to 12 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS42438
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1500

LIST OF FIGURES
LIST OF TABLES
DS646DB2
Figure 1. Advanced Register Tab - CS42438 ................................................................................. 7
Figure 2. Advanced Register Tab - FPGA ...................................................................................... 8
Figure 3. Internal Sub-Clock Routing ............................................................................................ 10
Figure 4. Internal Data Routing ..................................................................................................... 11
Figure 5. TDMer ............................................................................................................................ 12
Figure 6. External MCLK Control .................................................................................................. 13
Figure 7. Block Diagram................................................................................................................ 29
Figure 8. CS42438 ........................................................................................................................ 30
Figure 9. DSP Header................................................................................................................... 31
Figure 10. S/PDIF Input ................................................................................................................ 32
Figure 11. S/PDIF Output.............................................................................................................. 33
Figure 12. FPGA ........................................................................................................................... 34
Figure 13. FPGA Connections ...................................................................................................... 35
Figure 14. Control Port.................................................................................................................. 36
Figure 15. Control Port Connections............................................................................................. 37
Figure 16. Analog Input 1-2........................................................................................................... 38
Figure 17. Analog Input 3-4........................................................................................................... 39
Figure 18. Analog Input 5.............................................................................................................. 40
Figure 19. Analog Input 6.............................................................................................................. 41
Figure 20. Analog Input 7-8........................................................................................................... 42
Figure 21. Analog Output 1-2........................................................................................................ 43
Figure 22. Analog Output 3-4........................................................................................................ 44
Figure 23. Analog Output 5-6........................................................................................................ 45
Figure 24. Analog Output 7-8........................................................................................................ 46
Figure 25. Power........................................................................................................................... 47
Figure 26. Silk Screen................................................................................................................... 48
Figure 27. Top side Layer ............................................................................................................. 49
Figure 28. Bottom side Layer ........................................................................................................ 50
Table 1. Data to SDIN ................................................................................................................... 16
Table 2. Clocks toCODEC ............................................................................................................ 17
Table 3. Data to CS8406............................................................................................................... 17
Table 4. Data to DSP .................................................................................................................... 20
Table 5. System Connections ....................................................................................................... 27
Table 6. Jumper Settings .............................................................................................................. 28
Table 7. Revision History .............................................................................................................. 51
CDB42438
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