S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 19

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

5: PINS
5.2 Pin Description
5.2.1
1-10
Pin Names
AB[16:1]
DB[15:0]
WE0#
AB0
Key:
I
O
IO
P
C
CS
COx
TSx
CNx
TEST
Host Interface
=
=
=
=
=
=
=
=
=
=
Type
IO
I
I
I
Input
Output
Bi-Directional (Input/Output)
Power pin
CMOS level input
CMOS level Schmitt input
CMOS output driver, x denotes driver type (see I
Tri-state CMOS output driver, x denotes driver type (see I
page 1-16)
CMOS low-noise output driver, x denotes driver type (see I
page 1-16)
CMOS level test input with pull down resistor
3, 4, 5, 6, 7,
8, 9, 11, 12,
45, 53, 54,
55, 56, 57,
58, 59, 62,
63, 64, 65,
66, 67, 68,
13, 14, 15,
16, 17, 18,
Pin #
70
69
19
77
Table 5-1 Host Interface Pin Descriptions
C/TS2
Cell
CS
CS
C
RESET#
State
Input
Input
Input
Hi-Z
EPSON
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs system address bit 0 (A0).
• For MC68K #1, this pin inputs the lower data strobe (LDS#).
• For MC68K #2, this pin inputs system address bit 0 (A0).
• For Generic #1, this pin inputs system address bit 0 (A0).
• For Generic #2, this pin inputs system address bit 0 (A0).
See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for
summary.
These pins input the system address bits 16 through 1 (A[16:1]).
These pins have multiple functions.
• For SH-3/SH-4 mode, these pins are connected to [D15:0].
• For MC68K #1, these pins are connected to D[15:0].
• For MC68K #2, these pins are connected to D[31:16] for a 32-bit
• For Generic #1, these pins are connected to D[15:0].
• For Generic #2, these pins are connected to D[15:0].
See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for
summary.
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs the write enable signal for the
• For MC68K #1, this pin must be tied to IO V
• For MC68K #2, this pin inputs the bus size bit 0 (SIZ0).
• For Generic #1, this pin inputs the write enable signal for the lower
• For Generic #2, this pin inputs the write enable signal (WE#)
See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for
summary.
device (e.g. MC68030) or D[15:0] for a 16-bit device (e.g.
MC68340).
lower data byte (WE0#).
data byte (WE0#).
OL
/I
OH
in Table 6-4: “Output Specifications,” on page 1-16)
OL
OL
/I
/I
OH
OH
S1D13705F00A HARDWARE FUNCTIONAL
in Table 6-4: “Output Specifications,” on
in Table 6-4: “Output Specifications,” on
Description
SPECIFICATION (X27A-A-001-06)
DD