S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 207

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

1: INTERFACING TO THE MOTOROLA MC68328 “DRAGONBALL” MICROPROCESSOR
Using The Generic #1 Host Bus Interface
5-6
If UDS# and/or LDS# are required for their alternate IO functions, then the MC68328 to S1D13705
interface may be implemented using the S1D13705 Generic #1 host bus interface. Note that in either
case, the DTACK# signal must be made available for the S1D13705, since it inserts a variable
number of wait states depending upon CPU/LCD synchronization and the LCD panel display mode.
WAIT# must be inverted (using an inverter enabled by CS#) to make it an active high signal and thus
compatible with the MC68328 architecture. A single resistor is used to speed up the rise time of the
WAIT# (DTACK#) signal when terminating the bus cycle.
The following diagram shows a typical implementation of the MC68328 to S1D13705 using the
Generic #1 host bus interface.
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 1-2 Typical Implementation of MC68328 to S1D13705 Interface - Generic #1
MC68328
DTACK#
UWE#
CLK0
D[15:0]
A[16:0]
LWE#
CSB3
OE#
EPSON
System RESET
Vcc
470
S1D13705F00A APPLICATION NOTES
WAIT#
WE0#
AB[16:0]
DB[15:0]
RD/WR#
RD#
BUSCLK
WE1#
RESET#
CS#
BS#
S1D13705
(X27A-G-007-01)