S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 211

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR
Burst Cycles
5-10
Figure 2-2 “Power PC Memory Write Cycle” illustrates a typical memory write cycle on the Power
PC system bus.
If an error occurs, TEA (Transfer Error Acknowledge) is asserted and the bus cycle is aborted. For
example, a peripheral device may assert TEA if a parity error is detected, or the MPC821 bus
controller may assert TEA if no peripheral device responds at the addressed memory location within
a bus time-out period.
For 32-bit transfers, all data lines (D[0:31]) are used and the two low-order address lines A30 and
A31 are ignored. For 16-bit transfers, data lines D0 through D15 are used and address line A30 is
ignored. For 8-bit transfers, data lines D0 through D7 are used and all address lines (A[0:31]) are
used.
Note: This assumes that the Power PC core is operating in big endian mode (typically the case for
Burst memory cycles are used to fill on-chip cache memory and to carry out certain on-chip DMA
operations. They are very similar to normal bus cycles with the following exceptions:
• Always 32-bit.
• Always attempt to transfer four 32-bit words sequentially.
• Always address longword-aligned memory (i.e. A30 and A31 are always 0:0).
• Do not increment address bits A28 and A29 between successive transfers; the addressed device
If a peripheral is not capable of supporting burst cycles, it can assert Burst Inhibit (BI)
simultaneously with TA, and the processor will revert to normal bus cycles for the remaining data
transfers.
Burst cycles are mainly intended to facilitate cache line fills from program or data memory. They are
normally not used for transfers to/from IO peripheral devices such as the S1D13705, therefore the
interfaces described in this document do not attempt to support burst cycles. However, the example
interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is
accidently enabled for the S1D13705 address space.
must increment these address bits internally.
embedded systems).
TSIZ[0:1], AT[0:3]
SYSCLK
RD/WR
D[0:31]
A[0:31]
Transfer Start
TS
TA
Figure 2-2 Power PC Memory Write Cycle
Valid
Wait States
EPSON
Complete
Transfer
S1D13705F00A APPLICATION NOTES
Next Transfer
Starts
(X27A-G-010-01)