S1D15206F00A200 Epson, S1D15206F00A200 Datasheet - Page 518

• Manufacturer Part Number: S1D15206F00A200
• Description: LCD Drivers LCD DRIVER
• Manufacturer: Epson

Specifications of S1D15206F00A200

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S1D15A06 Series
Oscillation circuit
The S1D15A06 series generates display clocks using its
built-in CR oscillation circuit. The built-in oscillation
circuit is enabled when CL = HIGH is selected and the
power save mode is turned off.
Table 7 shows relationship between frequency of exter-
nal clock (f
and f
Display timing generator circuit
The display timing generator circuit generates the timing
signal to the line address circuit and the display data
latch circuit, and generates COM scan signal and the
LCD AC signal (dual-frame AC driver waveform).
12–14
FR
.
Table 6
Table 7
S1D15A06
Clock input
CL
), frequency of built-in clock circuit (f
HIGH
LOW
CL
*****
When built-in oscillation circuit is used
When external clock input is used
Built-in CR oscillation circuit is turned off [display clock is turned off].
Item
Built-in CR oscillation circuit is enabled.
OSC
External clock input mode
EPSON
)
Operation
You can stop operation of the CR oscillation circuit by
selecting CL = LOW. Display clock can be externally
entered via CL pin (when external clock is turned off,
CL pin must be placed in LOW).
Since CL pin is used for resetting the built-in CR clock
circuit, it must satisfy the f
"DC Characteristics".
LCD driver circuits
These are multiplexers outputting the LCD panel driving
4-level signal which level is determined by a combination
of display data, COM scan signal, and LCD AC signal
(FR). Figure 6 shows an example of SEG and COM
output waveforms.
f
FR
f
f
FR
FR
computation formula
=f
=f
OSC
CL
/ (55 16) [Hz]
/ (55 8) [Hz]
CL
requirements given in the
Rev. 1.0a