S1D15206F00A200 Epson, S1D15206F00A200 Datasheet - Page 95

no-image

S1D15206F00A200

Manufacturer Part Number
S1D15206F00A200
Description
LCD Drivers LCD DRIVER
Manufacturer
Epson
Datasheet

Specifications of S1D15206F00A200

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S1D15206F00A200
Manufacturer:
EPSON/爱普生
Quantity:
20 000
Relationship between display data RAM and addresses (if initial display line is 08):
Display Timing Generator Circuit
This section explains how the display timing generator circuit
operates.
Signal generation to line counter and display data latch
circuit
The line address counter, RAM, and latch circuit of the S1D15206
series operate synchronous to the display clock (the oscillator circuit
outp).mm The LCD drive signal is sent to LCD panel driver output
pin SEGn.
Rev.3.5
D2,D1,D0
=0,0,0
0,0,1
0,1,0
0,1,1
1,0,0
Page
address
Column
address
SEGOUT
A
D
C
Data
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D0=0
D0=1
00
4F 4E 4D 4C 4B 4A 49 48
0 1 2 3 4 5 6 7
01020304 0506 07
EPSON
Figure 4
Page 0
Page 1
Page 2
Page 3
Page 4
The timing of LCD panel driver outputs is independent of the timing
of RAM data input from microprocessor.
LCD AC Signal (FR)
The LCD AC signal, FR, is generated from the display clock. The
FR controller generates dual-frame AC driver waveforms for LCD
panel driver circuit.
4D 4E
02
77
01
78
00
79
4F
Line
address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Start
1/16
1/8
S1D15206 Series
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM S
COM
output
4–11

Related parts for S1D15206F00A200