S1D15206F00A200 Epson, S1D15206F00A200 Datasheet - Page 571

• Manufacturer Part Number: S1D15206F00A200
• Description: LCD Drivers LCD DRIVER
• Manufacturer: Epson

Specifications of S1D15206F00A200

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S1D15B01 Series
* V
* The Capacitance depend on the load of the LCD panel to be driven. Set a value that LCD driver voltage may be stable
Voltage regulator circuit
The boosting voltage occurring at the V
to the voltage regulator, and the V
voltage) is output.
Because the S1D15B01 series has the high-accuracy
constant voltage source, the 32-level electronic volume
function and the internal resistor for the V
regulator (= V
high-accuracy voltage regulator circuit without external
component. And V
commands only to adjust the LCD contrast.
(A) When the V
Through the use of the V
volume function, V
commands only (without adding any external resistors).
The V
13–16
(reference value = 1.0 to 4.7 F).
DD2
V
OUT
0
voltage must be set so that V
voltage can be calculated using the following
V
+
+
+
+
+
Quintuple Boosting
Quintuple Boosting
DD2
= 5 x V
V
= 13.5V
SS
= 2.7V
= 0V
0
DD2
-resistor), it is possible to construct a
0
-resistor is used.
V
V
CAP3+
CAP1–
CAP1+
CAP4+
CAP2–
CAP2+
DD2
OUT
0
0
or V
voltage can be controlled by
voltage can be adjusted by
SS
0
-resistor and the electronic
V
OUT
0
voltage (LCD driver
+
+
+
+
V
Quadruple Boosting
Quadruple Boosting
DD2
= 4 x V
V
OUT
= 10.8V
SS
= 2.7V
OUT
= 0V
voltage does not exceed the absolute maximum rated value.
DD2
V
V
CAP3+
CAP1–
CAP1+
CAP4+
CAP2–
CAP2+
pin is sent
DD2
OUT
0
voltage
or V
SS
EPSON
Figure 8
V
OUT
V
+
+
+
DD2
equations within the range of V
V
7 at Ta=25 C.
= 3 x V
V
Triple Boosting
Triple Boosting
REG
SS
Table 7
= 2.7V
= 8.1V
S1D15B01
V
= 0V
DD2
0
is the on-chip constant voltage as shown in Table
V
V
CAP3+
CAP1–
CAP1+
CAP4+
CAP2–
CAP2+
Model
= (1+Rb/Ra)•V
DD2
OUT
V
EV
or V
*****
= (1– /200) •V
SS
V
1.3V
V
OUT
EV
REG
OPEN
+
+
V
DD2
= 2 x V
Double boosting
Double boosting
V
SS
= 2.7V
= 5.4V
Thermal Gradient
REG
= 0V
0
DD2
< V
V
V
CAP3+
CAP1–
CAP1+
CAP4+
CAP2–
CAP2+
–0.05%/ C
DD2
OUT
(Equation A-1)
OUT
or V
.
SS
Rev. 1.1a