S1D15206F00A200 Epson, S1D15206F00A200 Datasheet - Page 549

• Manufacturer Part Number: S1D15206F00A200
• Description: LCD Drivers LCD DRIVER
• Manufacturer: Epson

Specifications of S1D15206F00A200

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

*1. This is in the case of making the access by WR and RD, setting the CS1=LOW.
*2. This is in the case of making the access by CS1, setting the WR, RD=LOW.
*3. The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns. When using the system cycle
*4. All timings are specified based on the 20 and 80% of V
*5. t
Rev. 1.0a
Table 27
Address hold time
Address setup time
System cycle time
Control LOW pulse width(Write)
Control LOW pulse width(Read)
Control HIGH pulse width(Write)
Control HIGH pulse width(Read)
Data setup time
Data hold time
Access time
Output disable time
time at high speed, they are specified for (tr+tf) < = (t
the LOW level.
CCLW
and t
Item
CCLR
are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and WR,RD are at
D7 to D0
Signal
WR
WR
RD
RD
A0
Symbol
EPSON
t
t
t
t
t
t
CCHW
t
CCLW
CCHR
t
t
CYC8
CCLR
t
t
ACC8
AW8
DH8
OH8
AH8
DS8
CYC8
DD
-t
.
CCLW
Condition
CL=100pF
) or (tr+tf) < = (t
[V
DD
=1.8V to 2.7V, Ta=–40 to 85 C]
CYC8
1000
Min.
150
300
150
150
120
10
0
0
0
–
-t
CCLR
S1D15A06 Series
-t
CCHR
Max.
260
200
–
–
–
–
–
–
–
–
–
).
Units
ns
12–45