DS33X42DK Maxim Integrated Products, DS33X42DK Datasheet - Page 336

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DS33X42DK

Manufacturer Part Number
DS33X42DK
Description
Power Management Modules & Development Tools Ethernet Over PDH Ma PDH Mapping Devices
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS33X42DK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
11.4 MII/RMII and GMII Interfaces
In GMII Mode, TX_EN is high with the first bit of the preamble. For 10Mbps operation, the data bit outputs are
updated every 10 clocks.
Figure 11-18. GMII Transmit Interface Functional Timing
GMII Receive data on RXD[1:0] is expected to be synchronous with the rising edge of ______. The data is only
valid if RX_CRS is high. The external PHY asynchronously drives RX_CRS low during carrier loss.
Figure 11-19. GMII Receive Interface Functional Timing
Rev: 063008
RX_CRS
TXD[1:0
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
REF_CLK
REF_CLK
TX_E
RXD[1:0]
N
]
P
P
R
R
E
E
A
A
M
M
B
B
L
L
E
E
F
F
C
C
S
S
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