DS33X42DK Maxim Integrated Products, DS33X42DK Datasheet - Page 7
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DS33X42DK
Manufacturer Part Number
DS33X42DK
Description
Power Management Modules & Development Tools Ethernet Over PDH Ma PDH Mapping Devices
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33X11.pdf
(375 pages)
Specifications of DS33X42DK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Figure 11-19. GMII Receive Interface Functional Timing ........................................................................................ 336
Figure 11-20. MII Transmit Functional Timing......................................................................................................... 337
Figure 11-21. MII Transmit Half Duplex with a Collision Functional Timing ............................................................ 337
Figure 11-22. MII Receive Functional Timing.......................................................................................................... 337
Figure 11-23. RMII Transmit Interface Functional Timing ....................................................................................... 338
Figure 11-24. RMII Receive Interface Functional Timing ........................................................................................ 338
Figure 12-1. Transmit GMII Interface Timing........................................................................................................... 342
Figure 12-2. Receive GMII Interface Timing............................................................................................................ 343
Figure 12-3. Transmit MII Interface Timing ............................................................................................................. 344
Figure 12-4. Receive MII Interface Timing .............................................................................................................. 345
Figure 12-5. Transmit RMII Interface Timing........................................................................................................... 346
Figure 12-6. Receive RMII Interface Timing............................................................................................................ 347
Figure 12-7. MDIO Interface Timing ........................................................................................................................ 348
Figure 12-8. Transmit WAN Timing (Noninverted TCLK) ........................................................................................ 349
Figure 12-9. Receive WAN Timing (Noninverted RCLK) ........................................................................................ 350
Figure 12-10. Transmit Voice Port Interface Timing................................................................................................ 351
Figure 12-11. Receive Voice Port Interface Timing................................................................................................. 352
Figure 12-12. DDR SDRAM Interface Timing.......................................................................................................... 354
Figure 12-13. Intel Bus Read Timing (MODE = 0) .................................................................................................. 356
Figure 12-14. Intel Bus Write Timing (MODE = 0)................................................................................................... 356
Figure 12-15. Motorola Bus Read Timing (MODE = 1) ........................................................................................... 357
Figure 12-16. Motorola Bus Write Timing (MODE = 1) ........................................................................................... 357
Figure 12-17. Multiplexed Intel Bus Read Timing (MODE = 0) ............................................................................... 359
Figure 12-18. Multiplexed Intel Bus Write Timing (MODE = 0) ............................................................................... 359
Figure 12-19. Multiplexed Motorola Bus Read Timing (MODE = 1)........................................................................ 360
Figure 12-20. Multiplexed Motorola Bus Write Timing (MODE = 1) ........................................................................ 360
Figure 12-21. SPI Interface Timing Diagram ........................................................................................................... 361
Figure 12-22. JTAG Interface Timing ...................................................................................................................... 362
Figure 13-1. JTAG Functional Block Diagram ......................................................................................................... 363
Figure 13-2. TAP Controller State Diagram............................................................................................................. 366
Figure 13-3. JTAG Functional Timing...................................................................................................................... 369
Rev: 063008
7 of 375
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