STEVAL-ISV009V1 STMicroelectronics, STEVAL-ISV009V1 Datasheet - Page 24

• Manufacturer Part Number: STEVAL-ISV009V1
• Description: Power Management Modules & Development Tools DUAL STG DC/AC CNVRT DEMO BRD
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STEVAL-ISV009V1

• Design Resources: STEVAL-ISV009V1 BOM STEVAL-ISV009V1 Schematic
• Main Purpose: DC/DC, Step Up
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: 36V
• Current - Output: -
• Voltage - Input: -
• Regulator Topology: Boost
• Frequency - Switching: -
• Board Type: Fully Populated
• Utilized Ic / Part: SPV1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Voltage regulation
10.4
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SPV1020 implements an internal control guaranteeing the current balance among the 4
branches, monitoring the current flowing on each branch with a maximum offset of 350mA.
SPI, serial peripheral interface
The SPV1020 embeds a 4-pin compatible SPI interface. The SPI allows full duplex,
synchronous, serial communication between a host controller (the master) and the
SPV1020 peripheral device (the slave). SPV1020 provides the following 4 pins:
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●
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Figure 21. SPI interface: master slaves connection example
The SPI master selects one of the slaves and provides the synchronizing clock and starts all
the communications. The idle state of the serial clock for the SPV1020 is high, while data
pins are driven on the falling edges of the serial clock and they are sampled on its rising
edges (SPI control bits CPOL=1, and CPHA=1). The bit order of each byte is MSB first.
When the master initiates a transmission, a data byte is shifted out through the MOSI pin to
the slave, while another data byte is shifted out through the MISO pin to the master; the
master controls the serial clock on the SCLK pin. The SS (active low) pin must be driven low
by the master during each transmission.
XCS (or SS),
SPI_CLOCK (or SCLK),
SPI_DATA_IN (or MOSI),
SPI_DATA_OUT (or MISO).
Doc ID XXXXX Rev 1
AN3392