LFE2-50E-D-EVN Lattice, LFE2-50E-D-EVN Datasheet - Page 24

• Manufacturer Part Number: LFE2-50E-D-EVN
• Description: MCU, MPU & DSP Development Tools LatticeMico32/DSP DEV BD/LatticeECP2
• Manufacturer: Lattice

Specifications of LFE2-50E-D-EVN

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 31. Control Signals of the Flash Chips U0402 and U0403
SPI Flash
The LatticeECP2-50 FPGA is an SRAM-based programmable device, and is therefore volatile. In order for it to be
automatically configured upon power-up, a non-volatile 16 Mbit SPI Flash device is provided. The SPI Flash can be
programmed with configuration bitstream data. The SPI Flash can be configured either through the ispDOWN-
LOAD connector or via the integrated USB configuration interface.
Table 32. FPGA to SPI Flash Connections
To program the SPI Flash configuration device, use the FPGA Loader function of the ispVM System software. The
FPGA Loader programming scheme provides an in-system JTAG programming method for configuration devices.
The FPGA acts as a bridge between the JTAG interface and the SPI interface of the serial configuration device.
Configure the SPI Flash as follows:
1. In the ispVM System software, choose Edit -> Add Device to open the Device Information dialog box.
2. Click Select to open the Select Device dialog box. Select device family LatticeECP2, device LFE2-50E, and
3. Change the Device Access Options to SPI Flash Programming.
4. Select Flash Device : STMicro SPI-M25P16 and click OK.
5. Browse Data File: Select the ECP2-50 bitstream to program into the SPI PROM, click OK.
6. Click OK to close the SPI Serial Flash Device dialog.
7. Click OK to close the Device Information dialog
8. Click GO. The ispVM System software programs the SPI Flash via the FPGA.
9. Disconnect and then reconnect the power supply. The FPGA will take about three seconds to be programmed
Power Supply
Power is supplied via a 2.1 mm DC power jack in the top left corner of the board. The board is protected against
reversed power supply. The input supply is 5V DC.
package 672 fpBGA from the drop-down lists.
by the SPI Flash.
Flash Pin
34
32
14
53
Note: The SPI CLK pin can be connected to FPGA E19. This allows the LatticeMico32 to access the SPI PROM for
data retrieval/storage purposes. On revision B boards, CLK is E17.
SPI Pin
HOLDn
WPn
CLK
CS
DI
Q
MEMORY_OE#
FLASH_RESET
FLASH_BYTE#
Signal Name
FLASH_CE#
Signal Name
CSSPIN
HOLD#
SPIDO
CCLK
SISPI
WP#
FPGA Pin
D13
A13
B14
B12
FPGA Port Name
HOLDJ
SCK
WPJ
CEJ
SO
24
SI
Flash Pin
LatticeMico32/DSP Development Board
13
16
17
FPGA Direction
Output
Output
Output
Output
Output
Input
for LatticeECP2 User’s Guide
FLASH_RY/BY#_A
FLASH_WP#/ACC
MEMORY_WE#
Signal Name
AA25 (FPGA NC)
AB26 (FPGA NC)
FPGA Pin
NC/E19
W23
V22
Y25
1
FPGA Pin
C13
A12
A14