LFE2-50E-D-EVN Lattice, LFE2-50E-D-EVN Datasheet - Page 6

• Manufacturer Part Number: LFE2-50E-D-EVN
• Description: MCU, MPU & DSP Development Tools LatticeMico32/DSP DEV BD/LatticeECP2
• Manufacturer: Lattice

Specifications of LFE2-50E-D-EVN

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Audio Interface
The audio interface has two connectors for 3.5 mm stereo jacks. The upper one is for line-out, the lower for line-in.
They are connected to the audio codec LM4549B by National Semiconductor.
Table 2. Audio Codec U1001 Pin Definitions
Detailed information on the audio codec can be found at the National Semiconductor website at www.national.com.
Clock Sources
A 25MHz oscillator supplies the FPGA (pin AD15), the CPLD (pin A8), the Ethernet controller and the Expansion
Connector (pin 29 of X12). The frequency can be measured via testpoint CLK. To generate other clock frequencies
use the PLLs of the FPGA. You can find detailed information on the usage of the PLLs on the Lattice website and in
the
The USB controller requires a 24MHz quartz for configuration. Another 12MHz quartz supplies the USB
host/peripheral controller.
Note: Since the Ethernet controller demands a 25MHz clock, no other basic clock can be used. Use the PLLs of the
FPGA to generate custom frequencies.
DDR SODIMM Socket for DDR SDRAM Modules
The board includes a standard DDR1 SODIMM socket with 200 contacts (DDR SDRAM Module is not included).
The upper four bytes of the data bus (D[63:32]) are not connected. Thus, only half of the capacity of the memory
module is available.
The DDR SODIMM socket is factory configured to provide a regulated 2.5V. DDR400 modules require a power
supply of 2.6V (±0.1V). Using a jumper on connector X21 (below the 5V power supply jack), the DDR power supply
can be changed to suit the needs of DDR400 modules.
Note: If you want to use the DDR SDRAM interface with a 16-bit data bus, provide your HDL design with an addi-
tional input port that is assigned to pin P9 of bank 6 (connected to schematic net DDR_VREF).
Do not use this signal in your design. Deactivate the internal pull-up of the pin in the ispLEVER software. It safe-
guards the DDR RAM memory from getting an incorrect supply voltage which will happen when the pin is unused
at a data bus width of 16 bits.
When using a 32-bit data bus, you do not have to assign this pin—ispLEVER will take care of it automatically.
LatticeECP2/M Family Data
Pin
10
6
2
8
AC97_BITCLK
AC97_EXT_CLK
AC97_SDATA_IN
AC97_SYNC
Signal Name
Sheet.
FPGA Pin
D25
C26
D24
B24
6
Pin
47
11
5
LatticeMico32/DSP Development Board
AC97_EAPD
AC97_RESET#
AC97_SDATA_OUT
Signal Name
for LatticeECP2 User’s Guide
FPGA Pin
C23
B25
C25