LFE2-50E-D-EVN Lattice, LFE2-50E-D-EVN Datasheet - Page 32

• Manufacturer Part Number: LFE2-50E-D-EVN
• Description: MCU, MPU & DSP Development Tools LatticeMico32/DSP DEV BD/LatticeECP2
• Manufacturer: Lattice

Specifications of LFE2-50E-D-EVN

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 33. Pin Table (Continued)
D19
E19
D15
A16
B16
E16
A17
B17
C17
T21
T22
G26
G25
G24
H26
H25
H24
H23
J22
K24
J24
R24
R23
R22
R21
P23
P22
P21
N22
H13
H14
A20
B20
C22
D22
A23
B23
E23
A24
C20
D20
E20
A21
B21
Pin Name
BB3V3_IO20
BB3V3_IO21
BB3V3_IO3
BB3V3_IO4
BB3V3_IO5
BB3V3_IO6
BB3V3_IO7
BB3V3_IO8
BB3V3_IO9
I2C_SCL1
I2C_SDA1
TST_COL0
TST_COL1
TST_COL2
TST_ROW0
TST_ROW1
TST_ROW2
TST_ROW3
LCD_ENABLE
LCD_REGSEL
LCD_RW
LED0#
LED1#
LED2#
LED3#
LED4#
LED5#
LED6#
LED7#
MACHXO_CLK0
MACHXO_CLK1
MACHXO_IO0
MACHXO_IO1
MACHXO_IO10
MACHXO_IO11
MACHXO_IO12
MACHXO_IO13
MACHXO_IO14
MACHXO_IO15
MACHXO_IO2
MACHXO_IO3
MACHXO_IO4
MACHXO_IO5
MACHXO_IO6
Signal Name
32
LatticeMico32/DSP Development Board
for LatticeECP2 User’s Guide
FPGA Prototyping Area
FPGA Prototyping Area
FPGA Prototyping Area
FPGA Prototyping Area
FPGA Prototyping Area
FPGA Prototyping Area
FPGA Prototyping Area
FPGA Prototyping Area
FPGA Prototyping Area
I
I
Key Matrix
Key Matrix
Key Matrix
Key Matrix
Key Matrix
Key Matrix
Key Matrix
LCD
LCD
LCD
LED
LED
LED
LED
LED
LED
LED
LED
MachXO
MachXO
MachXO
MachXO
MachXO
MachXO
MachXO
MachXO
MachXO
MachXO
MachXO
MachXO
MachXO
MachXO
MachXO
2
2
C EEPROM
C EEPROM
Area