LFE2-50E-D-EVN Lattice, LFE2-50E-D-EVN Datasheet - Page 35

• Manufacturer Part Number: LFE2-50E-D-EVN
• Description: MCU, MPU & DSP Development Tools LatticeMico32/DSP DEV BD/LatticeECP2
• Manufacturer: Lattice

Specifications of LFE2-50E-D-EVN

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Revision History
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
Portions copyright 2005 - 2008 Gleichmann and Company Electronics GmbH.
September 2007
February 2007
February 2008
February 2009
October 2008
October 2008
October 2008
August 2007
March 2007
March 2008
June 2008
June 2009
April 2007
April 2007
April 2007
April 2008
July 2007
Date
Version
01.0
01.1
01.2
01.3
01.4
01.5
01.6
01.7
01.8
01.9
02.0
02.1
02.2
02.3
02.4
02.5
02.6
Initial release.
Added Ordering Information section.
Updated SATA Interfaces information.
Reset Chip section - updated FPGA pin number for the the HPE RESET
signal.
Ordering information (EFUP) updated.
Added important information for proper connection of ispDOWNLOAD
(Programming) Cables.
Various minor updates to improve readability, and correct typographical
errors.
Updated information for pins 4-7 in the Expansion Connector X14 table.
Updated information for LRF pin TP0902 in the FPGA Connections for
the 12x12 Prototyping Area table.
Updated Ascynchronous SRAM text section and corresponding table.
Updated Parallel Flash text section.
Updated Ordering Information.
Corrected
Updated
Updated
Updated Peripheral Interfaces diagram with Board Version 2
information.
Updated Data Signal of the Asynchronous SRAM Chip U0404 table.
SPI Flash text section - Updated SPI Flash density to 16 bits. Added
table. Updated steps for programing the SPI Flash memory.
Added note to Parallel Flash text section.
Added Appendix B. Board Version 2 Schematics.
Address Signals of the Asynchronous SRAM Chips U0404 and
U0405 table -
MEMORY_A2.
Address Signals of the Flash Chips U0402 and U0403 table -
updated FPGA Pin information for MEMORY_A1 and MEMORY_A2.
Updated photo used in
Updated photo used in Components figure.
Updated Audio Interface text section.
Updated
35
7-Segment Display U0502 Pin Definition table.
Schematic Illustration of the Prototyping Area.
FPGA to SPI Flash Connections
Schematic Illustration of the Prototyping Area diagram.
LatticeMico32/DSP Development Board
updated FPGA Pin information for MEMORY_A1 and
User Interface Features figure.
Change Summary
for LatticeECP2 User’s Guide
table.