Core8051-M Actel, Core8051-M Datasheet
Core8051-M
Specifications of Core8051-M
Related parts for Core8051-M
Core8051-M Summary of contents
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... Core8051s v2.4 Handbook ...
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... Actel. Actel makes no warranties with respect to this documentation and disclaims any implied warranties of merchantability or fitness for a particular purpose. Information in this document is subject to change without notice. Actel assumes no responsibility for any errors that may appear in this document. This document contains confidential proprietary information that is not to be disclosed to any unauthorized person without prior written consent of Actel Corporation ...
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... Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Utilization and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 Core8051s Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 Supported Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Interface Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 Tool Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Example System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Synthesis in Libero IDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Place-and-Route in Libero IDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4 Core8051s Features Software Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 OCI Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Functional Ordered Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Hexadecimal Ordered Instructions ...
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... Serial channel • I/O ports • Timers The following set of 8051 microcontroller features are available in Core8051s, but are either optional or reduced in scope: • Multiply and divide instructions (MUL, DIV, and DA) – present by default, but may optionally be implemented as NOPs • Second data pointer (data pointer 1) – not enabled by default • ...
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... Table 7 on page 13 of Core8051s for each type of FPGA technology. These tables do not cover every possible configuration, but instead list a range of configurations which should give a good indication of the expected resource usage and performance of the core. Abbreviated versions of configuration options are used in the tables to aid readability ...
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... Registers Registers (FPGA tiles) are inferred for the 256x8 RAM during synthesis. Table 1 • Core8051s Utilization and Performance for IGLOO 1.2 V Devices (STD speed grade) None – – ujtag ujtag ujtag ujtag Yes 0 No ujtag Yes 1 No ujtag Yes 4 No None – ...
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... Introduction Table 2 • Core8051s Utilization and Performance for IGLOO 1.5 V Devices (STD speed grade) None – – ujtag ujtag ujtag ujtag Yes 0 No ujtag Yes 1 No ujtag Yes 4 No None – – Yes None – – No None – – No None – ...
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... Table 3 • Core8051s Utilization and Performance for Fusion, ProASIC3, and ProASIC3E Devices (–2 speed grade) None – – ujtag ujtag ujtag ujtag Yes 0 No ujtag Yes 1 No ujtag Yes 4 No None – – Yes None – – No None – – ...
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... Introduction Table 4 • Core8051s Utilization and Performance for ProASIC3L (–1 speed grade) None – – ujtag ujtag ujtag ujtag Yes 0 No ujtag Yes 1 No ujtag Yes 4 No None – – Yes None – – No None – – No None – – ...
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... Table 5 • Core8051s Utilization and Performance for ProASIC Configuration None – – UJTAG UJTAG UJTAG UJTAG Yes 0 No UJTAG Yes 1 No UJTAG Yes 4 No None - – Yes None - – No None - – No None - – No None - – No None - – No None - – No UJTAG ...
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... Introduction Table 6 • Core8051s Utilization and Performance for Axcelerator Devices (–2 speed grade) None – – I/Os Yes 0 No I/Os Yes 1 No I/Os Yes 4 No None – – Yes None – – No None – – No None – – No None – ...
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... Table 7 • Core8051s Utilization and Performance for RTAX-S Devices (–1 speed grade) None – – I/Os Yes 0 No I/Os Yes 1 No I/Os Yes 4 No None – – Yes None – – No None – – No None – – No None – ...
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... Table 1-1 shows the speed advantage of Core8051s over the standard Intel 8051. A speed advantage the first column means that Core8051s performs the same instruction 12 times faster than the standard Intel 8051. The second column in the given speed advantage. The third column lists the total number of instructions that have the given speed advantage ...
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... Supported Interfaces Ports The port signals of Core8051s are illustrated in Figure 2-1 • Core8051s I/O Signals Figure 2-1. Core8051s CLK PRESETN NSYSRESET WDOGRESN WDOGRES MOVX TDO TCK BREAKOUT TMS TRIGOUT TDI AUXOUT TRSTN DBGMEMPSWR MEMBANK BREAKIN MEMADDR MEMDATAI MEMDATAO MEMPSACKI MEMPSRD ...
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... Break bus input. When sampled high, a breakpoint is generated. If not used, connect to logic 0. High Break bus output. This is driven high when Core8051s stops emulation. This can be connected to an open-drain break bus that connects to multiple processors, so that when any CPU stops, all others on the bus are stopped within a few clock cycles ...
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... The read data bus is driven by the selected slave during read cycles (when PWRITE is low). The width of this bus matches the width of the widest peripheral in the system. The write data bus is driven by the Core8051s during write cycles (when PWRITE is high). The width of this bus matches the width of the widest peripheral in the system. ...
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... Supported Interfaces Interface Descriptions Parameters/Generics The Verilog parameters or VHDL generics shown in These may be modified by the user to configure Core8051s as required. When working with SmartDesign, these parameters/generics are set to appropriate values using the Core8051s configuration window. Table 2-2 • Table x. Core8051s Parameters/Generics Parameter/Generic ...
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... Environment (IDE) web repository. For information on using SmartDesign to instantiate, configure, connect, and generate cores, refer to the Libero IDE online help. The advanced peripheral bus (APB) version 3 interface of Core8051s will typically be connected to the mirrored master interface of CoreAPB3, with various APB or APB3 slaves connected to the slave interfaces of CoreAPB3 ...
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... Select Include trace RAM to include a 256-byte deep trace RAM within Core8051s. No trace RAM is present if this option is not selected. Including the trace RAM increases the tile count for the processor and consumes RAM blocks on the device. ...
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... RTL code to cause the synthesis tool to use registers (FPGA tiles) to implement the 256x8 internal RAM. This considerably increases the tile count for the core but has the benefit of enhancing the fault-tolerant capabilities of Core8051s. for more information on the APB interface. ...
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... Core8051s comes with a verification testbench and also supports bus functional model (BFM)-based simulation of a system in which it is instantiated. The BFM only simulates transactions on the APB interface of Core8051s and does implement a complete model of the processor not possible to simulate code running on the processor with a BFM-based simulation ...
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... APB bus, of which Core8051s is master. This verifies that the APB interface is fully operational. The BFM tests do not perform any verification on the Core8051s itself. The advantage of BFM-driven simulation is that you can exercise the system using a simple scripting language, before writing any C code or 8051 assembler code ...
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Tool Flows read This command causes the BFM to perform a read of a specified offset, within the memory map range of a specified system resource. Syntax read width resource_name byte_offset; • width: This takes on the enumerated values of ...
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... Synthesis button in the Project Manager. The Synthesis window appears, ® displaying the Synplicity Place-and-Route in Libero IDE After setting the design root appropriately and running synthesis, click the Layout button in the Project Manager to invoke Designer. Core8051s requires no special place-and-route settings. project. To perform synthesis, click the Run button Core8051s v2.4 Handbook 27 ...
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... Figure 4-1. Program Memory Core8051s can address kbytes of program memory space, from 0000H to FFFFH. The external memory bus interface (Table 4-1 on page active. Program memory is read when the CPU performs fetching instructions or MOVC. After reset, the CPU starts program execution from location 0000H. The lower part of the program memory includes interrupt and reset vectors ...
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... The width of the APB bus on Core8051s can be selected to match the width of the widest APB peripheral in the system (8, 16 bits). As the Core8051s is an 8-bit processor and it is not possible to indicate transaction size on the APB, reads and writes from or to the APB bus in 16-bit or 32- bit mode are accomplished by means of newly defined SFRs, hereafter referred registers ...
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... The next 16 bytes form a block of bit-addressable memory space at bit addressees 00H–7FH. SFR Registers The SFRs occupy the upper 128 bytes of internal data memory space. This SFR area is available only by direct addressing. Table 4-1 lists the SFR registers present in Core8051s. Table 4-1 • Core8051s SFR Registers Register Location SP ...
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... Core8051s Features Accumulator (acc) The acc register is the accumulator. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to the accumulator as A, not ACC. B Register (b) The b register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data ...
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... Interrupt 0 type control bit. This bit selects whether a rising edge or a high level on input pin INT0 causes an interrupt High level causes interrupt Rising edge causes interrupt Function Disable all interrupts 0 Unused 0 Unused 0 Unused 0 Unused Disable external interrupt 1 (INT1) 0 Unused Disable external interrupt 0 (INT0) Function Core8051s v2.4 Handbook 33 ...
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... Core8051s Features Interrupts Core8051s has two interrupt inputs, INT0 and INT1. INT0 is low priority (priority level 0), with a vector address of 03H. INT1 is high priority (priority level 1), with a vector address of 13H. Note: If using the Keil C51 C compiler, an interrupt function attribute of 0 must be used for INT0 and an attribute of 2 for INT1 ...
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... Instruction Set The Core8051s instructions are binary code compatible and perform the same functions as the industry- standard 8051. This is the ASM51 instruction set. Some of these instructions, however, are not enabled by default and so must be explicitly enabled if required. Table 5-1 and Table 5-2 ...
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Instruction Set Functional Ordered Instructions Table 5-3 through Table 5-7 on page 40 Table 5-3 • Arithmetic Instructions Mnemonic ADD A,Rn Adds the register to the accumulator. ADD A,direct Adds the direct byte to the accumulator. ADD A,@Ri Adds the ...
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... Clears the accumulator. CPL A Complements the accumulator Rotates the accumulator left. RLC A Rotates the accumulator left through carry Rotates the accumulator right. RRC A Rotates the accumulator right through carry. SWAP A Swaps nibbles within the accumulator. Description Core8051s v2.4 Handbook Byte Cycle ...
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Instruction Set Table 5-5 • Data Transfer Operations Mnemonic MOV A,Rn MOV A,direct MOV A,@Ri MOV A,#data MOV Rn,A MOV Rn,direct MOV Rn,#data MOV direct,A MOV direct,Rn MOV direct,direct MOV direct,@Ri MOV direct,#data MOV @Ri,A MOV @Ri,direct MOV @Ri,#data MOV ...
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... AND complements of direct bit to the carry. ORL C,bit OR direct bit to the carry flag. ORL C,bit OR complements of direct bit to the carry. MOV C,bit Moves the direct bit to the carry flag. MOV bit, C Moves the carry flag to the direct bit. Description Core8051s v2.4 Handbook Byte Cycle ...
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Instruction Set Table 5-7 • Program Branch Operations Mnemonic ACALL addr11 LCALL addr16 RET Return RETI Return AJMP addr11 LJMP addr16 SJMP rel JMP @A + DPTR JZ rel JNZ rel JC rel JNC rel JB bit,rel JNB bit,rel JBC ...
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... Hexadecimal Ordered Instructions The Core8051s instructions are listed in Table 5-8 • Core8051s Instruction Set in Hexadecimal Order Opcode 00H NOP 01H AJMP addr11 02H LJMP addr16 03H RR A 04H INC A 05H INC direct 06H INC @R0 07H INC @R1 08H INC R0 09H INC R1 0AH ...
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... Instruction Set Table 5-8 • Core8051s Instruction Set in Hexadecimal Order (continued) Opcode 40H JC rel 41H AJMP addr11 42H ORL direct,A 43H ORL direct,#data 44H ORL A,#data 45H ORL A,direct 46H ORL A,@R0 47H ORL A,@R1 48H ORL A,R0 49H ORL A,R1 ...
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... Table 5-8 • Core8051s Instruction Set in Hexadecimal Order (continued) Opcode Mnemonic 80H SJMP rel 81H AJMP addr11 82H ANL C,bit 83H MOVC A,@A+ PC 84H DIV AB 85H MOV direct,direct 86H MOV direct,@R0 87H MOV direct,@R1 88H MOV direct,R0 89H MOV direct,R1 8AH ...
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... Instruction Set Table 5-8 • Core8051s Instruction Set in Hexadecimal Order (continued) Opcode C0H PUSH direct C1H AJMP addr11 C2H CLR bit C3H CLR C C4H SWAP A C5H XCH A,direct C6H XCH A,@R0 C7H XCH A,@R1 C8H XCH A,R0 C9H XCH A,R1 CAH ...
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... Instruction Definitions All Core8051s core instructions can be condensed to 53 basic operations, alphabetically ordered according to the operation mnemonic section, as shown in Table 5-9 • PSW Flag Modification (CY, OV, AC) Instruction CY ADD X ADDC X SUBB X MUL 0 DIV RRC X RLC X CJNE X Note: In this table, ‘X’ denotes that the indicated flag is affected by the instruction and can be a logic 1 or logic 0, depending upon specific calculations ...
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... Large Model In the large model, all variables, by default, reside in external data memory (which may kbytes). In the case of Core8051s, this covers 60 kbytes of external RAM and 4 kbytes of memory- mapped peripherals. The data pointer (DPTR) is used to address external memory, which results in slower accesses to variables than in the small model likely, however, that the large model is the more appropriate of the two for targeting Core8051s without having to use language extensions, as this allows the peripheral resources to be mapped as C variables ...
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... The following sizes are used: Table 5-12 • Size of Standard C data Types for 8051 Compilers Data Type char int long Table 5-10 summarizes some of the memory type Description Bytes 1 2 Size (bits Core8051s v2.4 Handbook Value Range 255 0 to 65535 47 ...
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... Core8051s. To achieve better system performance and smaller code size, however, the user may utilize language extensions specified by the C compiler. C Header Files reg51.h A customized version of the reg51.h file is required when compiling C code for Core8051s. This contains the following:" /*-------------------------------------------------------------------------- reg51.h Header file for Actel Core8051s microcontroller. ...
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... B = 0xF0; /* BIT Register */ /* PSW */ sbit CY = 0xD7; sbit AC = 0xD6; sbit F0 = 0xD5; sbit RS1 = 0xD4; sbit RS0 = 0xD3; sbit OV = 0xD2; sbit P = 0xD0; #endif " stdio.h Core8051s requires a custom-designed stdio library doesn't contain the serial channel normally found in 8051-based microcontrollers Core8051s v2.4 Handbook 49 ...
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... A program memory read cycle without wait states is shown in have been taken from the Figure 6-1 to Figure 6-14 on page 57. Description 150 ns 100 Sample Sample Sample Read Read Read Sample Sample Sample ( Figure 6-3 Figure 6-4 on page 53. Figure 6-1 Core8051 Datasheet. The following 200 ns 300 ns 250 ns 51 ...
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Instruction Timing clk memaddr memrd memwr mempsrd mempswr mempsack memdatao memdatai Figure 6-2 • Program Memory Fetch Cycle With Wait States clk memaddr N memrd memwr mempsrd mempswr mempsack memdatao memdatai (N) ...
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... Data shows an external data memory read cycle without stretch cycles. 100 ns 150 Addr Max. 1 × Tclk Data ( Read Read Sample Sample Core8051s v2.4 Handbook 250 ns 300 ns 350 Sample Sample Sample Read Sample Read Sample ( Figure 6-5 through Figure 6-12 on 200 ns 250 ns ...
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Instruction Timing clk memaddr N memrd memwr mempsrd mempswr mempsack memdatao memdatai Figure 6-6 • External Data Memory Read Cycle With One Stretch Cycle clk memaddr N memrd memwr mempsrd memdatao memdatai ...
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... Figure 6-9 • External Data Memory Write Cycle Without Stretch Cycles 150 ns 200 ns 250 ns 300 ns Addr Max. 8 × Tclk Data 100 ns 150 ns Addr Data Read Sample Core8051s v2.4 Handbook 400 ns 450 ns 350 Read Read Sample Sample 200 ns 250 Write Sample ( Read Sample ...
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Instruction Timing clk memaddr N memrd memwr mempsrd memdatao memdatai Figure 6-10 • External Data Memory Write Cycle With One Stretch Cycle clk memaddr memrd memwr mempsrd memdatao memdatai (N) Figure 6-11 ...
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... Figure 6-14 • APB Read Transfer Bus Cycle 200 ns 300 ns Addr Data Figure 6-13 and 100 ns 150 ns 200 ns 250 ns Addr 1 Data 1 100 ns 150 ns 200 ns 250 ns Addr 1 Data Core8051s v2.4 Handbook 400 ns 500 Write Sample ( Read Sample Figure 6-14. 350 ns 400 ns 300 ns 350 ns 400 ns 300 ns 57 ...
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... Control Register (icon)" section register implements a subset of the Timer Control (TCON) register. In Table 5-8 • Core8051s Instruction Set in Hexadecimal was corrected. It had previously been listed as "ASH." The corrected from "BSH." A footnote was added to the table stating that the A5H opcode is used as a trap instruction for the implementation of software breakpoints ...
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... Many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the Actel web site. Website You can browse a variety of technical and non-technical information on Actel’s home page, at www.actel.com. Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center from 7:00 a ...
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... The phone hours are from 7:00 a.m. to 6:00 p.m., Pacific Time, Monday through Friday. The Technical Support numbers are: 650.318.4460 800.262.1060 Customers needing assistance outside the US time zones can either contact technical support via email (tech@actel.com) or contact a local sales office. Sales office listings can be found on the website at www.actel.com/company/contact/default.aspx visio n 2 ...
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... Index A Actel electronic mail 61 telephone 62 web-based technical support 61 website header files 48 contacting Actel customer service 61 electronic mail 61 telephone 62 web-based technical support 61 customer service 61 E external data memory space 30 G generics 20 I instruction definitions 45 instruction set 35 instruction timing 51 internal data memory space ...
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... Fax +44 (0) 1276 607 540 © 2010 Actel Corporation. All rights reserved. Actel, Actel Fusion, IGLOO, Libero, Pigeon Point, ProASIC, SmartFusion and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. ...